CY14C101J Datasheet, PDF (5/32 Pages) Cypress Semiconductor – 1 Mbit (128 K × 8) Serial (I2C) nvSRAM

PRELIMINARY
CY14C101J
CY14B101J, CY14E101J
Data Validity
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH, that is, START and STOP condition.
The START and STOP conditions are generated by the master
to signal the beginning and end of a communication sequence
on the I²C bus.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I²C begins
with the master generating a START condition.
STOP Condition (P)
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
If an Repeated START condition is generated instead of a Stop
condition the bus continues to be busy. The ongoing transaction
on the I²C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 4. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
S
START Condition
SCL
P
STOP Condition
handbook, full pagewidth
SDA
MSB
SCL
S
or
Sr
1
2
START or
Repeated START
condition
Figure 5. Data Transfer on the I²C Bus
Acknowledgement
signal from slave
P
Acknowledgement ^Sr
signal from receiver
7
8
9
ACK
Byte complete,
interrupt within slave
1
2
3-8
9
ACK
Clock line held LOW while
interrupts are serviced
Sr
or
P
STOP or
Repeated START
condition
Byte Format
Each operation in I²C is done using 8 bit words. The bits are sent in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
An operation continues till a NACK is sent by the receiver or STOP or Repeated START condition is generated by the master The
SDA line must remain stable when the clock (SCL) is HIGH except for a START or STOP condition.
Document #: 001-54050 Rev. *D
Page 5 of 32
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