CY14C101J Datasheet, PDF (17/32 Pages) Cypress Semiconductor – 1 Mbit (128 K × 8) Serial (I2C) nvSRAM

PRELIMINARY
CY14C101J
CY14B101J, CY14E101J
Device ID Read
Device ID is a 4 byte code consisting of JEDEC assigned manufacturer ID, product ID, density ID, and die revision. These registers
are set in factory and are read only registers for the user.
Table 7. Device ID
Bits
#of Bits
Device
CY14C101J1
CY14C101J2
CY14C101J3
CY14B101J1
CY14B101J2
CY14B101J3
CY14E101J1
CY14E101J2
CY14E101J3
31 - 21
(11 bits)
Manufacture ID
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
20 - 7
(14 bits)
Product
ID
00001001000001
00001101000000
00001101000001
00001001010001
00001101010000
00001101010001
00001001100001
00001101100000
00001101100001
6- 3
(4 bits)
Density
ID
0100
0100
0100
0100
0100
0100
0100
0100
0100
2-0
(3 bits)
Die Rev
000
000
000
000
000
000
000
000
000
The device ID is divided into four parts as shown in Table 7:
1. Manufacturer ID (11 bits)
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
Cypress manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is given as:
Cypress ID - 000_0011_0100
2. Product ID (14 bits)
The product ID for device is shown in the Table 7.
3. Density ID (4 bits)
The 4 bit density ID is used as shown in Table 7 for indicating the
1 Mb density of the product.
4. Die Rev (3 bits)
Executing Commands Using Command
Register
The Control Registers Slave allows different commands to be
executed by writing the specific command byte in the command
register (0xAA). The command byte codes for each command
are specified in Table 6. During the execution of these
commands the device is not accessible and returns NACK if any
of the two slave devices is selected. If an invalid command is sent
by the master, nvSRAM responds with a NACK indicating that
command was not successful. The address latch of this slave
continues to point to the command register address. This
location can be read back to identify the data byte that was
written to the nvSRAM.
A read access to the command register is allowed and a burst
read would loop back to the first address in the array (0x00).
During execution of any command, the address counter retain
their value.
This is used to represent any major change in the design of the
product. The initial setting of this is always 0x0.
Figure 29. Command Execution using Command Register
By Master
SDA Line
By nvSRAM
S
T
A
Control Register
R
Slave Address
T
S 0 0 1 1 A2 A1 X 0
Command Register Address
1 01 0 1 0 10
A
A
Command Byte
S
T
O
P
P
A
Document #: 001-54050 Rev. *D
Page 17 of 32
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