CY14B101LA Datasheet, PDF (5/24 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM

PRELIMINARY
CY14B101LA, CY14B101NA
During any STORE operation, regardless of how it is initiated,
the CY14B101LA/CY14B101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14B101LA/CY14B101NA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V_CC< V_SWITCH), an internal RECALL request is latched. When
V_CC again exceeds the sense voltage of V_SWITCH, a RECALL
cycle is automatically initiated and takes t_HRECALL to complete.
During this time, HSB is driven low by the HSB driver.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B101LA/CY14B101NA
Software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 2. Mode Selection
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t_STORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t_RECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
CE
WE
OE, BHE, BLE^[3]
A₁₅ - A₀^[9]
Mode
I/O
Power
H
X
X
X
Not Selected Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
Read SRAM
Output Data
Active^[10]
0xB1C7
Read SRAM
Output Data
0x83E0
Read SRAM
Output Data
0x7C1F
Read SRAM
Output Data
0x703F
Read SRAM
Output Data
0x8B45
AutoStore
Output Data
Disable
Notes
9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A₁₄ - A₂) are used to control software modes.
Rest of the address lines are don’t care.
10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-42879 Rev. *C
Page 5 of 24
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