C9950 Datasheet, PDF (5/7 Pages) Cypress Semiconductor – 3.3V, 180-MHz, Multi-Output Clock Driver

C9950
Maximum Ratings^[5]
Maximum Input Voltage Relative to V_SS: ............ V_SS – 0.3V
Maximum Input Voltage Relative to V_DD:............. V_DD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD protection .............................................. 2 KV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V_in and V_out should be constrained to the
range:
V_SS < (V_in or V_out) < V_DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V_SS or V_DD).
DC Parameters: V_DD = V_DDC = 3.3V ±5%, T_A = –40°C to +85°C
Parameter
Description
V_IL
V_IH
I_IL
I_IH
V_OL
V_OH
I_DDC
I_DD
C_in
Input Low Voltage
Input High Voltage
Input Low Current (@V_IL = V_SS)
Input High Current (@V_IL =V_DD)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
PLL Supply Current
Input Capacitance
Conditions
Note 6
Note 6
I_OL = 40 mA, Note 7
I_OH = –40 mA, Note 7
All V_DDC and V_DD
V^DD only
Min.
2.0
2.4
Typ.
15
15
Max. Unit
0.8
V
V
–120
µA
120
µA
0.5
V
V
20
mA
20
mA
4
pF
AC Parameters^[8]: V_DD = V_DDC = 3.3V ±5%, T_A = –40°C to +85°C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Tr/Tf
TCLK Input Rise/Fall
3.0
ns
Fref
Reference Input Frequency
Note 9
Note 2
MHz
Fxtal
Crystal Oscillator Frequency
See Table 3 for details
10
25
MHz
FrefDC
Reference Input Duty Cycle
25
75
%
Fvco
PLL VCO Lock Range
200
480
MHz
Tlock
Maximum PLL lock Time
Tr/Tf
Output Clocks Rise/Fall Time^[10]
0.8V to 2.0V
0.10
10
ms
1.0
ns
Fout
Maximum Output Frequency
QA = (÷2)
180
MHz
QA/QB = (÷4)
120
QB = (÷8)
60
FoutDC
Output Duty Cycle
TCYCLE/2 – 1
TCYCLE/2 + 1 ns
tpZL, tpZH Output enable time (all outputs)
6
ns
tpLZ, tpHZ
TCCJ
TSKEW0
Output disable time (all outputs)
Cycle to Cycle Jitter (peak to peak)^[10]
Any Output to Any Output Skew^[10]
7
ns
±100
ps
200
350
ps
Notes:
5. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Inputs have internal pull-up/pull-down resistors that affect input current.
7. Driving series or parallel terminated 50Ω (or 50Ω to V_DD/2) transmission. Output buffers are dual staged to control drive strength in order to reduce over / under
shoot.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. Maximum and minimum input reference is limited by the VCO lock range.
10. Outputs loaded with 30 pF each.
Document #: 38-07072 Rev. *C
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