C9950 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 3.3V, 180-MHz, Multi-Output Clock Driver

C9950
3.3V, 180-MHz, Multi-Output Clock Driver
Product Features
• 180-MHz Clock Support
• Supports PowerPC™, Intel^®, and RISC Processors
• 9 Clock Outputs: Frequency Configurable
• Oscillator or Crystal Reference Input
• Output Disable Control
• Spread Spectrum Compatible
• Pin Compatible with MPC950
• Industrial Temp. Range: –40°C to +85°C
• 32-Pin TQFP Package
Block Diagram
Table 1. Frequency Table^[1]
FB_SEL = 1
FB_SEL = 1
SEL
QC QD
QC QD
(A:D) QA QB (0,1) (0:4) QA QB (0,1) (0:4)
0000 4x 2x 2x 2x 8x 4x 4x 4x
0001 4x 2x 2x x 8x 4x 4x 2x
0010 4x 2x x 2x 8x 4x 2x 4x
0011 4x 2x x
x 8x 4x 2x 2x
0100 4x x 2x 2x 8x 2x 4x 4x
0101 4x x 2x x 8x 2x 4x 2x
0110 4x x x 2x 8x 2x 2x 4x
0111 4x x x
x 8x 2x 2x 2x
1000 2x 2x 2x 2x 4x 4x 4x 4x
1001 2x 2x 2x x 4x 4x 4x 2x
1010 2x 2x x 2x 4x 4x 2x 4x
1011 2x 2x x
x 4x 4x 2x 2x
1100 2x x 2x 2x 4x 2x 4x 4x
1101 2x x 2x x 4x 2x 4x 2x
1110 2x x x 2x 4x 2x 2x 4x
1111 2x x x
x 4x 2x 2x 2x
Note:
1. x = is the reference input frequency
Pin Configuration
SELA
PLL_EN
TCLK
REF_SEL
XIN
XOUT
OSC
Phase
Detector
VCO
200-
480MHz
FB_SEL
SELB
SELC
MR/OE#
LPF
8/ 16
Power-On Reset
SELD
2/ 4
4/ 8
4/ 8
4/ 8
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
VDD 1
FB_SEL 2
SELA 3
SELB 4
SELC 5
SELD 6
VSS 7
XIN 8
C9950
24 QC0
23 VDDC
22 QC1
21 VSS
20 QD0
19 VDDC
18 QD1
17 VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07072 Rev. *C
Revised December 21, 2002