S26KL512S Datasheet, PDF (49/98 Pages) Cypress Semiconductor – 512 Mbit (64 Mbyte), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V

S26KL512S / S26KS512S
S26KL256S / S26KS256S
S26KL128S / S26KS128S
RWDS Stall
The RWDS Stall Control Bit in xVCR1[4] can be used to enable RWDS stall when a two bit error is encountered. If Dual Error Detect
(DED) is enabled (xVCR1[5] = 0) the RWDS Stall Control Bit will indicate whether RWDS will be held Low during a DED occurring in
the main array. If enabled (xVCR[2] = 0), upon DED, the RWDS will be driven Low. RWDS will remain in the Low state as long as
CS# remains asserted, normal RWDS functionality resumes as soon as CS# returns High. If the RWDS Stall Control Bit is in the
disabled state (xVCR[2] = 1) RWDS behavior is not impacted.
6.3 Data Protection
6.3.1
Secure Silicon Region
Each device has a 1024-byte one-time programmable Secure Silicon Region (SSR) address space that is separate from the Flash
Memory Array. The SSR area is divided into 32, individually lockable, 32-byte aligned and length regions.
In the 32-byte region starting at address zero:
 The 16 lowest address bytes are programmed by Cypress with a 128-bit random number. Only Cypress is able to program these
bytes. Attempting to program 0s into these locations will fail and generate a Program Status Error (SR[4] = 1).
 The next 4 higher address bytes (SSR Lock Bytes) are used to provide one bit per SSR region to permanently protect each region
from programming. The bytes are erased when shipped from Cypress. After an SSR region is programmed, it can be locked to
prevent further programming, by programming the related protection bit in the SSR Lock Bytes.
 The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes may be
programmed by the host system but it must be understood that a future device may use those bits for protection of a larger SSR
space. The bytes are erased when shipped from Cypress.
The remaining regions are erased when shipped from Cypress, and are available for programming of additional permanent data.
Refer to Figure 18, SSR Address Space on page 50 for a pictorial representation of the SSR memory space.
The SSR memory space is intended for increased system security. SSR values, such as the random number programmed by
Cypress, can be used to ‘mate’ a flash component with the system CPU / ASIC to prevent device substitution.
The configuration register SSR Freeze (xVCR10) bit protects the entire SSR memory space from programming when cleared (or
programmed for NVCR) to 0. This allows trusted boot code to control programming of SSR regions then set the Freeze bit to prevent
further SSR memory space programming during the remainder of normal power-on system operation.
6.3.1.1
Reading the Secure Silicon Region Memory Space
Reading the SSR Region is performed once the SSR ASO is entered using the SSR entry sequence. The SSR is mapped to a
specific sector identified during the SSR Entry command sequence. SSR Read operations within the sector identified during the
SSR Entry command sequence but outside the valid 8-kB SSR address range will yield indeterminate data. Reads to sectors not
overlaid by the SSR ASO will retrieve array data. A SSR Exit sequence will return the device to the array read ASO.
6.3.1.2
Programming Secure Silicon Region Memory Space
Programming the SSR memory is performed once the SSR ASO is entered using the SSR Entry sequence. The protocol of the SSR
programming command is the same as normal array programming. The SSR programing sequences can be issued multiple times to
any given SSR address, but this address space can never be erased. The valid address range for SSR Program is depicted in
Figure 18, SSR Address Space on page 50. SSR Program operations outside the valid SSR address range will ignore address A9
and higher and will alias into the valid SSR address range. SSR Program operations while Freeze = 0 will fail with no indication of
the failure. The SSR address space is not protected by the selection of an ASP Protection Mode. The Freeze SSR bit (xVCR.10)
may be used to protect the SSR address space. A SSR Exit sequence will return the device to the Read Mode.
Document Number: 001-99198 Rev. *F
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