S26KL512S Datasheet, PDF (1/98 Pages) Cypress Semiconductor – 512 Mbit (64 Mbyte), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V

S26KL512S / S26KS512S
S26KL256S / S26KS256S
S26KL128S / S26KS128S
512 Mbit (64 Mbyte), 256 Mbit (32 Mbyte),
128 Mbit (16 Mbyte) 1.8V/3.0V
HyperFlash™ Family
Features
 3.0V I/O, 11 bus signals
– Single ended clock
 1.8V I/O, 12 bus signals
– Differential clock (CK, CK#)
 Chip Select (CS#)
 8-bit data bus (DQ[7:0])
 Read-Write Data Strobe (RWDS)
– HyperFlash™ memories use RWDS only as a Read Data
Strobe
 Up to 333 MB/s sustained read throughput
 Double-Data Rate (DDR) – two data transfers per clock
 166-MHz clock rate (333 MB/s) at 1.8V V_CC
 100-MHz clock rate (200 MB/s) at 3.0V V_CC
 96-ns initial random read access time
– Initial random access read latency: 5 to 16 clock cycles
 Sequential burst transactions
 Configurable Burst Characteristics
– Wrapped burst lengths:
– 16 bytes (8 clocks)
– 32 bytes (16 clocks)
– 64 bytes (32 clocks)
– Linear burst
– Hybrid option — one wrapped burst followed by linear burst
– Wrapped or linear burst type selected in each transaction
– Configurable output drive strength
 Low Power Modes
– Active Clock Stop During Read: 12 mA, no wake-up
required
– Standby: 25 µA (typical), no wake-up required
– Deep Power-Down: 8 µA (typical)
– 300 µs wake-up required
 INT# output to generate external interrupt
– Busy to Ready Transition
– ECC detection
 RSTO# output to generate system level power-on reset
– User configurable RSTO# Low period
 512-byte Program Buffer
 Sector Erase
– Uniform 256-kB sectors
– Optional Eight 4-kB Parameter Sectors (32 kB total)
 Advanced Sector Protection
– Volatile and non-volatile protection methods for each
sector
 Separate 1024-byte one-time program array
 Operating Temperature
– Industrial (–40°C to +85°C)
– Industrial Plus (–40°C to +105°C)
– Extended (–40°C to +125°C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
 ISO/TS16949 and AEC Q100 Certified
 Endurance
– 100,000 program/erase cycles
 Retention
– 20 year data retention
 Erase and Program Current
– Max Peak  100 mA
 Packaging Options
– 24-Ball FBGA
 Additional Features
– ECC 1-bit correction, 2-bit detection
– CRC (Check-value Calculation)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-99198 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 25, 2016