CY7C66013C Datasheet, PDF (49/61 Pages) Cypress Semiconductor – Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub

CY7C66013C
CY7C66113C
Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend)
Properties of Incoming Packet
SETUP (if accepting SETUPs)
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
See
Table 16-1
See
Table 16-1
token count buffer dval
Setup <= 10 data valid
Setup > 10 junk x
DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr
updates 1
updates 1
UC UC 1 0 0 0 1 ACK
yes
updates updates updates 1
UC UC UC No Changeignore
yes
See
Setup x
Table 16-1
junk invalid updates 0
updates 1
UC UC UC No Changeignore
yes
Properties of Incoming Packet
Mode Bits token count buffer dval
DISABLED
Changes made by SIE to Internal Registers and Mode Bits
DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr
00 00 x
x
Nak In/Out
0 0 0 1 Out x
0 0 0 1 In x
Ignore In/Out
UC x
UC x
UC x
UC UC UC UC UC UC UC No Changeignore
no
UC UC UC UC UC 1 UC No ChangeNAK
yes
UC UC UC UC 1 UC UC No ChangeNAK
yes
0 1 0 0 Out x
0 1 0 0 In x
UC x
UC x
UC UC UC UC UC UC UC No Changeignore
no
UC UC UC UC UC UC UC No Changeignore
no
Stall In/Out
0 0 1 1 Out x
0 0 1 1 In x
UC x
UC x
Properties of Incoming Packet
UC UC UC UC UC 1 UC No ChangeStall
yes
UC UC UC UC 1 UC UC No ChangeStall
yes
CONTROL WRITE
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr
Normal Out/premature status In
1 0 1 1 Out <= 10 data valid updates 1
updates UC UC 1 1 1 0 1 0 ACK
yes
1 0 1 1 Out > 10 junk x
updates updates updates UC UC 1 UC No Changeignore
yes
1 0 1 1 Out x
junk invalid updates 0
updates UC UC 1 UC No Changeignore
yes
1 0 1 1 In
x
UC
x
UC UC UC UC 1 UC 1 No ChangeTX 0
yes
NAK Out/premature status In
1 0 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC No ChangeNAK
yes
1 0 1 0 Out > 10 UC x
UC UC UC UC UC UC UC No Changeignore
no
1 0 1 0 Out x
UC invalid UC
UC UC UC UC UC UC No Changeignore
no
1 0 1 0 In
x
UC
x
UC UC UC UC 1 UC 1 No ChangeTX 0
yes
Status In/extra Out
0 1 1 0 Out <= 10 UC valid UC UC UC UC UC 1 UC 0 0 1 1 Stall
yes
0 1 1 0 Out
0 1 1 0 Out
0 1 1 0 In
> 10 UC
x
UC
x
UC
x
UC
invalid UC
x
UC
Properties of Incoming Packet
UC UC UC UC UC UC No Changeignore
no
UC UC UC UC UC UC No Changeignore
no
UC UC UC 1 UC 1 No ChangeTX 0
yes
CONTROL READ
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits token count buffer dval DTOG DVAL COUNT Setup In Out ACK Mode Bits Response Intr
Normal In/premature status Out
1 1 1 1 Out 2 UC valid 1
1
updates UC UC 1 1 No ChangeACK
yes
1 1 1 1 Out 2 UC valid 0
1
updates UC UC 1 UC 0 0 1 1 Stall
yes
1 1 1 1 Out !=2 UC valid updates 1
updates UC UC 1 UC 0 0 1 1 Stall
yes
1 1 1 1 Out > 10 UC x
UC UC UC UC UC UC UC No Changeignore
no
1 1 1 1 Out x
UC invalid UC
UC UC UC UC UC UC No Changeignore
no
Document #: 38-08024 Rev. *B
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