CY7C66013C Datasheet, PDF (33/61 Pages) Cypress Semiconductor – Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub

CY7C66013C
CY7C66113C
When servicing an interrupt, the hardware does the following:
1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register, Figure 15-1).
2. Clears the flip-flop of the current interrupt.
3. Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt
Vector, see Section 16.1).
The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user
can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited
only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1 Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed in Table 16-1. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I²C interrupt) has the lowest priority.
1
USB Reset Int
CLR
DQ
CLK
Enable [0]
(Reg 0x20)
1
AddrA ENP2 Int
CLR
DQ
CLK
Enable [2]
(Reg 0x21)
1
I²C Int
CLR
Q
D
CLK
Enable [6]
(Reg 0x20)
USB Reset Clear _Interrupt
USB Reset IRQ
128-µs CLR
128-µs IRQ
Vector
1-ms CLR
1-ms IRQ
AddrA EP0 CLR
AddrA EP0 IRQ
IRQout
AddrA EP1 CLR
AddrA EP1 IRQ
AddrA EP2 CLR
AddrA EP2 IRQ
AddrB EP0 CLR
AddrB EP0 IRQ
AddrB EP1 CLR
AddrB EP1 IRQ
Hub CLR
Hub IRQ
DAC CLR
DAC IRQ
GPIO/HAPI CLR
GPIO/HAPI IRQ
I²C CLR
I²C IRQ
Interrupt Priority Encoder
To CPU
CPU
IRQ Sense
IRQ
Global
Interrupt
Enable
Bit
CLR
Int Enable
Sense
Controlled by DI, EI, and
RETI Instructions
Interrupt
Acknowledge
Figure 16-3. Interrupt Controller Function Diagram
Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds
to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
Document #: 38-08024 Rev. *B
Page 33 of 61
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