CY14V101PS Datasheet, PDF(47/67 Page) Cypress Semiconductor – 1-Mbit (128K × 8) Quad SPI nvSRAM with Real Time Clock

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CY14V101PS Datasheet, PDF (47/67 Pages) Cypress Semiconductor – 1-Mbit (128K × 8) Quad SPI nvSRAM with Real Time Clock

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CY14V101PS

Figure 100. Watchdog Timer Block Diagram

Oscillator

32.768 KHz

Clock

Divider

32 Hz

Counter

1 Hz

Zero

Compare

WDF

WDS

Load

WDW

write to

Watchdog

Programmable Square Wave Generator

The square wave generator block uses the crystal output to

generate a desired frequency on the INT pin of the device. The

output frequency can be programmed to be one of these:

â 1 Hz

â 512 Hz

â 4096 Hz

â 32768 Hz

The square wave output is not generated while the device is

running on backup power.

Power Monitor

The device provides a power management scheme with power

fail interrupt capability. It also controls the internal switch to

backup power for the clock and protects the memory from low

VCC access. The power monitor is based on an internal band gap

reference circuit that compares the VCC voltage to VSWITCH

threshold.

As described in the section AutoStore Operation on page 6,

when VSWITCH is reached as VCC decays from power loss, a data

STORE operation is initiated from SRAM to the nonvolatile

elements, securing the last SRAM data state. Power is also

switched from VCC to the backup supply (battery) to operate the

RTC oscillator.

When operating from the backup source, read and write

operations to nvSRAM are inhibited and the RTC functions are

not available to the user. The RTC clock continues to operate in

the background. The updated RTC time keeping registers are

available to the user after VCC is restored to the device (see

AutoStore or Power-Up RECALL on page 59).

Backup Power Monitor

The device provides a backup power monitoring system which

detects the backup power (battery backup) failure. The backup

power fail flag (BPF) is issued on the next power-up in case of

backup power failure. The BPF flag is set in the event of backup

voltage falling lower than VBAKFAIL. The backup power is

monitored even while the RTC is running in backup mode. Low

voltage detected during backup mode is flagged through the BPF

flag. BPF can hold the data only until a defined low level of the

back-up voltage (VDR).

Interrupts

The CY14X101Q has a flags register, interrupt register, and

Interrupt logic that can signal interrupt to the microcontroller.

There are three potential sources for interrupt: watchdog timer,

power monitor, and alarm timer. Each of these can be individually

enabled to drive the INT pin by appropriate setting in the interrupt

flags register (0x00) that the host processor uses to determine

the cause of the interrupt. The INT pin driver has two bits that

specify its behavior when an interrupt occurs.

An Interrupt is raised only if both a flag is raised by one of the

three sources and the respective interrupt enable bit in interrupts

two programmable bits, H/L and P/L, determine the behavior of

the output pin driver on INT pin. These two bits are located in the

interrupt register and can be used to drive level or pulse mode

output from the INT pin. In pulse mode, the pulse width is

internally fixed at approximately 200 ms. This mode is intended

to reset a host microcontroller. In the level mode, the pin goes to

its active polarity until the flags register is read by the user. This

mode is used as an interrupt to a host microcontroller. The

control bits are summarized in the section Interrupt Register.

Interrupts are only generated while working on normal power and

are not triggered when system is running in backup power mode.

Note The device generates valid interrupts only after the Power

Up RECALL sequence is completed. All events on INT pin must

be ignored for tFA duration after power-up.

Interrupt Register

Watchdog Interrupt Enable (WIE): When set to â1â, the

watchdog timer drives the INT pin and an internal flag when a

watchdog timeout occurs. When WIE is set to â0â, the watchdog

timer only affects the WDF flag in flags register.

Alarm Interrupt Enable (AIE): When set to â1â, the alarm match

drives the INT pin and an internal flag. When AIE is set to â0â, the

alarm match only affects the AF flag in flags register.

Power Fail Interrupt Enable (PFE): When set to â1â, the power

fail monitor drives the pin and an internal flag. When PFE is set

to â0â, the power fail monitor only affects the PF flag in flags

Square Wave Enable (SQWE): When set to â1â, a square wave

of programmable frequency is generated on the INT pin. The

frequency is decided by the SQ1 and SQ0 bits of the interrupts

SQWE bit over rides all other interrupts. However, the CAL bit

will take precedence over the square wave generator. This bit

defaults to â0â from factory.

Document Number: 001-94176 Rev. *I

Page 47 of 67

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