CY14V101PS Datasheet, PDF (20/67 Pages) Cypress Semiconductor – 1-Mbit (128K × 8) Quad SPI nvSRAM with Real Time Clock

CY14V101PS
SPI Memory Read Instructions
Read instructions access the memory array. These instructions
cannot be used while a STORE or RECALL cycle is in progress.
A STORE cycle in progress is indicated by the WIP bit of the
Status Register and the HSB pin.
Read Instructions
The device performs the read operations when read instruction
opcodes are given on the SI pin and provides the read output
data on the SO pin for SPI mode or the I/O1, I/O0 pins for Dual
I/O Mode or the I/O3, I/O2, I/O1, and I/O0 pins for Quad I/O
Mode. After the CS pin is pulled LOW to select a device, the read
opcode is entered followed by three bytes of address. The device
contains a 17-bit address space for 1-Mbit configuration.
The most significant address byte contains A16 in bit 0 and other
bits as 'don't care'. Address bits A15 to A0 are sent in the
following two address bytes. After the last address bit is
transmitted, the data (D7-D0) at the specific address is shifted
out on the falling edge of SCK starting with D7. The reads can
be performed in burst mode if CS is held LOW.
The device automatically increments to the next higher address
after each byte of data is output. When the last data memory
address (0x1FFFF) is reached, the address rolls over to 0x00000
and the device continues the read instruction. The read
operation is terminated by driving CS HIGH at any time during
data output.
Note The Read instruction operates up to maximum of 40-MHz
frequency. In Dual and Quad I/O modes, dummy cycle is
required after the address bytes. This allows the device to
pre-fetch the first byte and start the pipeline flowing.
READ Instruction
READ instruction can be used in SPI, Dual I/O (DPI) or Qua I/O
(QPI) Modes. In SPI Mode, opcode and address bytes are trans-
mitted through SI pin, one bit per clock cycle. At the falling edge
of SCK of the last address cycle, the data (D7-D0) at the specific
address is shifted out on SO pin one bit per clock cycle starting
with D7.
In DPI Mode, opcode and address bytes are transmitted through
I/O1 and I/O0 pins, two bits per clock cycle. At the falling edge of
SCK after the last address cycle, the data (D7-D0) at the specific
address is shifted out two bits per clock cycle starting with D7 on
I/O1 and D6 on I/O0. In QPI Mode, opcode and address bytes
are transmitted through I/O3, I/O2, I/O1, and I/O0 pins, four bits
per clock cycle. At the falling edge of SCK of the last address
cycle, data (D7-D0) at the specific address is shifted out four bits
per clock cycle starting with D7 on I/O3, D6 on I/O2, D5 on I/O1,
and D4 on I/O0.
Figure 19. READ Instruction in SPI Mode
CS
SCK
SI
SO
X
0
0
0
0
0
0
1
1 A23 A22 A21 Am-3 A3 A2 A1 A0
X
D7 D6 D5 D4 D3 D2 D1 D0 ^hi-Z
Opcode (03h)
Address
Read data
Figure 20. Burst Mode READ Instruction in SPI Mode
CS
SCK
SI
SO
X
0
0
0
0
0
0
1
1 A23 A22 A21 Am-3 A3 A2 A1 A0
X
hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
X
D7 D6 D5 D4 D3 D2 D1 D0
hi-Z
Opcode (03h)
Address
Read data
Document Number: 001-94176 Rev. *I
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