CYWB022XX Datasheet, PDF (46/78 Pages) Cypress Semiconductor – West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller

CYWB022XX Family
Table 19. Asynchronous SRAM Mode Timing Parameters (continued)
Parameter
Description
Min
tAH
Address hold time from WE# or CE# end for PCRAM to SRAM changes (Astoria is
2
default in the PCRAM mode after RESET. This timing is the requirement for the first
time to access the P-Port Interface Configuration Register to change the Astoria to
PSRAM mode)
Address hold time from WE# or CE# end for PSRAM mode
0
tWP
WE# pulse width
22
tWPH
WE# HIGH time
10
tCPH
CE# HIGH time
10
tDS
Data setup to write end
18
tDH
Data hold from write end
0
tWHZ
Write to DQ High Z output
–
tOW
End of write to Low Z output
3
tDPW
DRQ# pulse width
110
Non Multiplexing Asynchronous SRAM Mode
Figure 30. Non Multiplexing Asynchronous SRAM Read Timing Parameters
Endpoint Read – Address Transition Controlled Timing (OE# is asserted )
tRC
ADDRESS
tAA
tOH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Max Unit
–
ns
–
–
ns
–
ns
–
ns
–
ns
–
ns
22.5
ns
–
ns
–
ns
OE# Controlled Timing
ADDRESS
CE#
OE#
DATA OUT
tRC
tEA
tOE
tOLZ
HIGH IMPEDANCE
tLZ
tHZ
tOHZ
DATA VALID
HIGH
IMPEDANCE
Document Number: 001-13805 Rev. *M
Page 46 of 78