CYWB022XX Datasheet, PDF(22/78 Page) Cypress Semiconductor – West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller

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CYWB022XX Datasheet, PDF (22/78 Pages) Cypress Semiconductor – West Bridge®: Astoria™ USB and Mass Storage Peripheral Controller

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CYWB022XX Family

Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments (continued)

Pin Name

Ball #

Double SDIO

Configuration

H2 SD_D[7]

I/O

SDIO & GPIO

Configuration

I/O SD_D[7]

I/O

GPIO

Configuration

I/O PD[7] (GPIO)

I/O

GPIF

Configuration

I/O GPIF_DATA [15]

I/O

GPIF & GPIO

Configuration

I/O PD[7] (GPIO)

H1 SD_D[6]

I/O SD_D[6]

I/O PD[6] (GPIO)

I/O GPIF_DATA [14] I/O PD[6] (GPIO)

G3 SD_D[5]

I/O SD_D[5]

I/O PD[5] (GPIO)

I/O GPIF_DATA [13] I/O PD[5] (GPIO)

G2 SD_D[4]

I/O SD_D[4]

I/O PD[4] (GPIO)

I/O GPIF_DATA [12] I/O PD[4] (GPIO)

F2 SD_D[3]

I/O SD_D[3]

I/O PD[3] (GPIO)

I/O GPIF_DATA [11] I/O PD[3] (GPIO)

F3 SD_D[2]

I/O SD_D[2]

I/O PD[2] (GPIO)

I/O GPIF_DATA [10] I/O PD[2] (GPIO)

E3 SD_D[1]

I/O SD_D[1]

I/O PD[1] (GPIO)

I/O GPIF_DATA [9] I/O PD[1] (GPIO)

E2 SD_D[0]

I/O SD_D[0]

I/O PD[0] (GPIO)

I/O GPIF_DATA [8] I/O PD[0] (GPIO)

G1 SD_CLK

F4 SD_CMD

J1 SD_POW

E1 SD_WP

H5 SD2_D[7]

O SD_CLK

I/O SD_CMD

O SD_POW

I SD_W

I/O PB[7] (GPIO)

PC-7 (GPIO)

I/O PC-3 (GPIO)

O PC-6 (GPIO)

I N/C

I/O PB[7] (GPIO)

I/O PC-7 (GPIO)

I/O PC-3 (GPIO)

I/O PC-6 (GPIO)

I N/C

I/O GPIF_DATA [7]

I/O PC-7 (GPIO)

I/O PC-3 (GPIO)

I/O PC-6 (GPIO)

I PC-5 (GPIO)

I/O GPIF_DATA [7]

J4 SD2_D[6]

I/O PB[6] (GPIO)

I/O GPIF_DATA [6] I/O GPIF_DATA [6]

G5 SD2_D[5]

I/O PB[5] (GPIO)

I/O GPIF_DATA [5] I/O GPIF_DATA [5]

H4 SD2_D[4]

I/O PB[4] (GPIO)

I/O GPIF_DATA [4] I/O GPIF_DATA [4]

J3 SD2_D[3]

I/O PB[3] (GPIO)

I/O GPIF_DATA [3] I/O GPIF_DATA [3]

G4 SD2_D[2]

I/O PB[2] (GPIO)

I/O GPIF_DATA [2] I/O GPIF_DATA [2]

H3 SD2_D[1]

I/O PB[1] (GPIO)

I/O GPIF_DATA [1] I/O GPIF_DATA [1]

J2 SD2_D[0]

I/O PB[0] (GPIO)

I/O GPIF_DATA [0] I/O GPIF_DATA [0]

F7 SD2_CLK

H6 SD2_CMD

G7 SD2_POW

J8 N/C

J5 N/C

G6 PA-5 (GPIO)

H7 N/C

J7 SD2_WP

O PA[6] (GPIO)

I/O PA[7] (GPIO)

O PC[0] (GPIO)

O N/C

I/O PA-5 (GPIO)

I N/C

O PC-2 (GPIO)

I/O PA[6] (GPIO)

I/O PA[7] (GPIO)

I/O PC[0] (GPIO)

O N/C

I/O PA-5 (GPIO)

I N/C

I/O PC-2 (GPIO)

I/O PA-6 (GPIO)

I/O PA-7 (GPIO)

I/O PC-0 (GPIO)

O GPIF_CTL[1]

O GPIF_CTL[0]

I/O PA-5 (GPIO)

I GPIF_RDY[0]

I/O PC-2 (GPIO)

I/O PA-6 (GPIO)

I/O PA-7 (GPIO)

I/O PC-0 (GPIO)

O GPIF_CTL[1]

O GPIF_CTL[0]

I/O PA-5 (GPIO)

O GPIF_RDY[0]

I/O PC-2 (GPIO)

C2 RESETOUT

O RESETOUT

D2 PC-5 (GPIO[1]) or I/O PC-5 (GPIO[1])

SD2_CD

I/O PC-5 (GPIO[1])

D1 PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0])

SD_CD

I SD_CD

C3 RESET#

D4 WAKEUP

O RESETOUT /

GPIF_RDY[1]

I/O PC-5 (GPIO[1])

I/O PC-4 (GPIO[0])

O RESETOUT /

GPIF_RDY[1]

I/O PC-5 (GPIO[1])

I/O PC-4 (GPIO[0])

Pin Description

Power

Domain

I/O

I/O SD Data or GPIO or SSVDDQ

GPIF Data

VGND

I/O SD Data or GPIO or

GPIF Data

I/O SD Data or GPIO or

GPIF Data

I/O SD Data or GPIO or

GPIF Data

I/O SD Data or GPIO or

GPIF Data

I/O SD Data or GPIO or

GPIF Data

I/O SD Data or GPIO or

GPIF Data

I/O SD Data or GPIO or

GPIF Data

I/O SD Clock or GPIO

I/O SD CMD or GPIO

I/O SD Power or GPIO

I/O SD Write Protect

I/O SD2 Data or GPIO or SNVDDQ

GPIF Data

VGND

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Data or GPIO or

GPIF Data

I/O SD2 Clock or GPIO

I/O SD2 CMD or GPIO

I/O SD2 Power or GPIO

O GPIF Control Signal

I/O GPIO

O GPIF Ready Signal

I/O SD Write Protect or

GPIO

O RESETOUT or GPIF GVDDQ

VGND

I/O GPIO or SD2 CD

I/O GPIO or SD CD

I RESET

I Wake Up Signal

Document Number: 001-13805 Rev. *M

Page 22 of 78

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