CY8CPLC20_12 Datasheet, PDF (41/56 Pages) Cypress Semiconductor – Powerline Communication Solution

CY8CPLC20
10. Packaging Information
This chapter illustrates the packaging specifications for the CY8CPLC20 PLC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the Emulator Pod Dimension drawings at http://www.cypress.com.
10.1 Packaging Dimensions
Figure 10-1. 28-Pin (210-Mil) SSOP
51-85079 *E
Document Number: 001-48325 Rev. *K
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