CY8CPLC20_12 Datasheet, PDF (37/56 Pages) Cypress Semiconductor – Powerline Communication Solution

CY8CPLC20
9.4.4 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C  T_A  85 C. Typical parameters are measured at 5 V at 25 C and are for design guidance only.
Table 9-2. AC Digital Block Specifications
Function
All functions
Description
Block input clock frequency
V_DD  4.75 V
Min Typ Max Unit
–
– 49.2 MHz
Notes
Timer
Input clock frequency
No capture, V_DD 4.75 V
With capture
Capture pulse width
–
– 49.2 MHz
–
– 24.6 MHz
50^[9]
–
–
ns
Counter
Input clock frequency
No enable input, V_DD  4.75 V
–
– 49.2 MHz
With enable input
–
– 24.6 MHz
Enable input pulse width
50^[9]
–
–
ns
Dead Band Kill pulse width
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
50^[9]
–
–
ns
Disable mode
50^[9]
–
–
ns
Input clock frequency
CRCPRS
(PRS Mode)
CRCPRS
(CRC Mode)
V_DD  4.75 V
Input clock frequency
V_DD  4.75 V
Input clock frequency
–
– 49.2 MHz
–
– 49.2 MHz
–
– 24.6 MHz
SPIM
Input clock frequency
–
–
8.2 MHz The SPI serial clock (SCLK) frequency is equal to the
input clock frequency divided by 2
SPIS
Input clock (SCLK) frequency
Width of SS_negated between
transmissions
–
–
50^[9]
–
4.1 MHz The input clock is the SPI SCLK in SPIS mode
–
ns
Transmitter
Receiver
Input clock frequency
V_DD  4.75 V, 2 stop bits
V_DD  4.75 V, 1 stop bit
Input clock frequency
The baud rate is equal to the input clock frequency
–
–
49.2 MHz ^{divided by 8}
–
– 24.6 MHz
The baud rate is equal to the input clock frequency
divided by 8
V_DD  4.75 V, 2 stop bits
V_DD  4.75 V, 1 stop bit
–
– 49.2 MHz
–
– 24.6 MHz
Note
9. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-48325 Rev. *K
Page 37 of 56