CYRF69303 Datasheet, PDF (40/70 Pages) Cypress Semiconductor – Programmable Radio-on-Chip LPstar

CYRF69303
Table 55. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
SPI Use
Int Enable Int Act Low Reserved
High Sink Open Drain
Pull-up
Enable
Output
Enable
Read/Write
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
These registers control the operation of pins P1.4–P1.6, respectively.
The P1.4–P1.6 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the
SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable bit
and the corresponding bit in the P1 data register.
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, High Sink, Open Drain, and Pull-up Enable
control the behavior of the pin.
The 50 mA sink drive capability is only available in the CY7C602xx. In the CY7C601xx, only 8 mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit.
Bit 7
SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
Bit 6
see Section Int Enable
Bit 5
see Section Int Act Low
Bit 4
Reserved
Bit 3
see Section High Sink
Bit 2
see Section Open Drain
Bit 1
see Section Pull-up Enable
Bit 0
see Section Output Enable
Note For Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 59 on page 43)
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of pins
P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set;
it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin
P1.4 must be configured as an input.
Table 56. P1.7 Configuration (P17CR) [0x14] [R/W]
Bit #
7
6
5
4
3
2
Field
Reserved Int Enable Int Act Low Reserved High Sink Open Drain
Read/Write
–
R/W
R/W
–
R/W
R/W
Default
0
0
0
0
0
0
This register controls the operation of pin P1.7.
50 mA sink drive capability is available. The P1.7 GPIO’s threshold is always set to TTL.
Bit 7
Reserved
Bit 6
Bit 5
see Section Int Enable
see Section Int Act Low
Bit 4
Reserved
Bit 3
see Section High Sink
Bit 2
see Section Open Drain
Bit 1
see Section Pull-up Enable
Bit 0
see Section Output Enable
1
Pull-up
Enable
R/W
0
0
Output
Enable
R/W
0
Document Number: 001-66502 Rev. *D
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