CYRF69303 Datasheet, PDF (18/70 Pages) Cypress Semiconductor – Programmable Radio-on-Chip LPstar

Data Memory Organization
The MCU function provides up to 256 bytes of data RAM.
Table 22. Data Memory Organization
after reset
8-bit PSP
Address
0x00
Stack begins here and grows upward
CYRF69303
Top of RAM Memory
0xFF
Flash
This section describes the Flash block of the CYRF69303. Much
of the user visible Flash functionality, including programming and
security, are implemented in the M8C Supervisory Read Only
Memory (SROM). CYRF69303 Flash has an endurance of 1000
cycles and 10-year data retention.
Flash Programming and Security
All Flash programming is performed by code in the SROM. The
registers that control the Flash programming are only visible to
the M8C CPU when it is executing out of SROM. This makes it
impossible to read, write, or erase the Flash by bypassing the
security mechanisms implemented in the SROM.
Customer firmware can only program the Flash through SROM
calls. The data or code images can be sourced by way of any
interface with the appropriate support firmware. This type of
programming requires a ‘bootloader’ — a piece of firmware
resident on the Flash. For safety reasons, this bootloader must
not be over written during firmware rewrites.
The Flash provides four auxiliary rows that are used to hold Flash
block protection flags, boot time calibration values, configuration
tables, and any device values. The routines for accessing these
auxiliary rows are documented in the SROM section. The
auxiliary rows are not affected by the device erase function.
In-System Programming
CYRF69303 enables this type of in-system programming by
using the P1.0 and P1.1 pins as the serial programming mode
interface. This allows an external controller to cause the
CYRF69303 to enter serial programming mode and then to use
the test queue to issue Flash access functions in the SROM.
SROM
The SROM holds code that is used to boot the part, calibrate
circuitry, and perform Flash operations (Table 23 lists the SROM
functions). The functions of the SROM may be accessed in
normal user code or operating from Flash. The SROM exists in
a separate memory space from user code. The SROM functions
are accessed by executing the Supervisory System Call
instruction (SSC), which has an opcode of 00h. Before executing
the SSC, the M8C’s accumulator needs to be loaded with the
desired SROM function code from Table 23. Undefined functions
causes a HALT if called from user code. The SROM functions
are executing code with calls; therefore, the functions require
stack space. With the exception of Reset, all of the SROM
functions have a parameter block in SRAM that must be
configured before executing the SSC. Table 24 on page 19 lists
all possible parameter block variables. The meaning of each
parameter, with regards to a specific SROM function, is
described later in this section.
Table 23. SROM Function Codes
Function Code
00h
01h
Function Name
SWBootReset
ReadBlock
02h
WriteBlock
03h
EraseBlock
05h
EraseAll
06h
TableRead
07h
CheckSum
Stack Space
0
7
10
9
11
3
3
Document Number: 001-66502 Rev. *D
Page 18 of 70