Z9952 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – 3.3V, 180MHz, Multi-Output Zero Delay Buffer

Z9952
3.3V, 180MHz, Multi-Output Zero Delay Buffer
AC Parameters¹
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONDITIONS
Freq
Reference Input Frequency
Note 2
Note 2
MHz
Fvco
PLL VCO Lock Range
200
480
MHz
Tlock
Tr / Tf
Maximum PLL lock Time
Output Clocks Rise / Fall Time^4,5
0.10
10
ms
1.0
ns
0.8V to 2.0V
Fout
Maximum Output Frequency
-
FoutDC
Output Duty Cycle^4,5
TCYCLE/2 –
750
180
120
80
TCYCLE/2 +
750
MHz
ps
QB, QC = (÷2)
QA, QB, QC = (÷4)
QA = (÷6)
tpZL, tpZH Output enable time (all outputs)
2
10
ns
tpLZ, tpHZ Output disable time (all outputs)
2
8
TCCJ
Cycle to Cycle Jitter (peak to peak)⁵
+/- 100
Tpd
REFCLK to FB_IN Delay^3,,4,5
-200
200
TSKEW0 Any Output to Any Output Skew^4,5
-
150
ns
ps
ps
ps
Same frequencies
250
Different frequencies
VDDA = VDD = VDDC = 3.3V +/- 5%, TA = -40°C to +85°C
Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with
loaded outputs.
Note 2: Maximum and minimum input reference is limited by the VCO lock range.
Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the
minimum limits with an increase/decrease of the input reference clock period.
Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2).
Note 5: Outputs loaded with 30pF each
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07085 Rev. *B
12/22/2002
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