CYIA2SC0300AA-BQE Datasheet, PDF (4/18 Pages) Cypress Semiconductor – 1/3” VGA-Format CMOS Image Sensor

3 Imager Array Description
Die photograph: A photograph of the IM103 die is shown in
Figure 4. Major features of interest include:
• Row control circuitry (to the left of the array as shown).
• Column amplifiers/correlated double sample circuits and
analog-to-digital converters, arranged above and below the
image sensor array.
• Data registers (arranged above/below the analog-to-digital
converters).
Image Array “Frame”: A schematic representation of the
array is shown in Figure 5.
Row drivers: As noted above, the row circuitry is located on
the left side of the array. This circuitry controls various
row-related signals (including the reset signal, the row select
signal, and the hard/soft reset signal). Timing for the row
drivers is controlled by SCLK.
Column circuitry/ADCs: The column amplifiers/CDS circuits
and analog-to-digital converters are located above and below
the sensor array. Each column has its own amplifier/CDS
circuit, while each ADC is shared between two columns.
Timing for column sampling and analog-to-digital conversion
is controlled by SCLK.
The location of the column amplifiers and ADCs alternates
between the top and bottom of the array, according to which
pair of columns is being read out. Columns 0, 1, 4, 5, …, 4n,
4n+1 use amplifiers and ADCs at the bottom of the array, while
columns 2, 3, 6, 7, …, 4n+2, 4n+3 use amplifiers and ADCs at
the top of the array.
CYIA2SC0300AA-BQE
Figure 4. IM103 Die Photograph Showing the Physical
Location of Major Functional Blocks
TO PIN 1
ROW 481
ROW 480
ROW 479
ROW 478
........ ........
ADC
MUX
CDS/AMP
........ ........
.......
Sensor Array
ROW 3
ROW 2
ROW 1
ROW 0
Input from register 0
........ ........
CDS/AMP
MUX
ADC
.......
CDS/AMP
MUX
ADC
Figure 5. Imager Frame, showing the row control shift register (to the left) and the column
amplifiers/MUXes/ADCs (top and bottom)
Document #: 001-11358 Rev. **
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