CYIA2SC0300AA-BQE Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 1/3” VGA-Format CMOS Image Sensor

CYIA2SC0300AA-BQE
1/3” VGA-Format CMOS Image Sensor
Features
• VGA Resolution
• 1/3” Optical Format
• Automotive Grade device
• 120 db Dynamic Range
• 60 PIN CBGA
• Low power dissipation
Functional Description
Cypress IM103 is Automotive grade CMOS Image Sensor with
high dynamic range (120 db). IM103 is built with Autobrite^®
technology useful for Automotive Vision Systems which
produce crisp clear video in visible and near IR wavelengths.
Device can be used for Lane departure working, Night Vision,
Adaptive Cruise control, driver drowsiness etc.
Introduction
This document describes the automotive grade IM103 1/3”
format VGA CMOS image sensor. The description covers:
• Architecture
• Operation
• Wide-dynamic-range capture
• Register settings
• Electrical and electro-optical specifications
This imager chip can be supplied in several different
configurations including:
• Monochrome or color pixel array
1 Sensor Architecture
The diagram in Figure 1 shows the major functional blocks of
the imager. These blocks include:
• Image sensor array
• Row control circuitry
• Column sense circuitry
• Analog-to-digital converters
• Timing and control logic
• Program registers
• Digital-output shift registers
Sensor array: The sensor array consists of an optically active
482 row X 642 column matrix, with 18 additional dark columns
on right side of the array (the array is described more fully in
section 3). Each sensing element (pixel) is 8 µm X 8 µm in size.
Timing and control circuitry: The sensor uses two clocks
(data strobe or DSTR, and system clock or SCLK). Data strobe
controls the timing of the output shift registers, while SCLK
controls exposure and data conversion timing. Clocking
details are given in section 5.
Column circuitry: The column circuitry includes a column
amplifier (with correlated double sampling [CDS] capability)
and a 12-bit analog-to-digital converter (ADC). Multiple ADCs
operate in parallel across the array.
Output registers: Data from the ADCs are shifted into a
parallel-in/serial-out 24-bit-wide row buffer. Data are shifted
out to the parallel data I/O from the buffer after each row of
data is converted.
ROW
SCLK
RESET
Sensor Array
D0
D1
D2
D3
D4
Column Amplifiers/CDS
D5
Analog/Digital Converters
D6
D7
Data Shift Registers
DSTR
WE
OE
Figure 1. IM103 Image Sensor Block Diagram.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-11358 Rev. **
Revised October 13, 2006