CY7C1561KV18_11 Datasheet, PDF (4/29 Pages) Cypress Semiconductor – 72-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
Contents
Pin Configuration ............................................................. 5
165-Ball FBGA (13 × 15 × 1.4 mm) Pinout.................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
Valid Data Indicator (QVLD)...................................... 10
PLL ............................................................................ 10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO)................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Boundary Scan Order .................................................... 19
Power-Up Sequence in QDR II+ SRAM ......................... 20
Power-Up Sequence ................................................. 20
PLL Constraints......................................................... 20
Maximum Ratings........................................................... 21
Operating Range............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics............................................... 21
DC Electrical Characteristics..................................... 21
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 23
Thermal Resistance........................................................ 23
Switching Characteristics.............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information...................................................... 26
Ordering Code Definition........................................... 26
Package Diagram............................................................ 27
Acronyms ........................................................................ 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Document Number: 001-15878 Rev. *L
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