CY7C1561KV18_11 Datasheet, PDF (1/29 Pages) Cypress Semiconductor – 72-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
72-Mbit QDR^® II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 550-MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5-clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ Quad data rate (QDR^®) II+ operates with 2.5-cycle read latency
when DOFF is asserted HIGH
■ Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
■ Available in ×8, ×9, and ×36 configurations
■ Full data coherency, providing most current data
■ Core V_DD = 1.8 V± 0.1 V; I/O V_DDQ = 1.4 V to V_DD ^[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
■ Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
With Read Cycle Latency of 2.5 cycles
CY7C1561KV18: 8M ×8
CY7C1576KV18: 8M × 9
CY7C1565KV18: 2M × 36
Functional Description
The CY7C1561KV18, CY7C1576KV18, and CY7C1565KV18
are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+ archi-
tecture has separate data inputs and data outputs to completely
eliminate the need to “turnaround” the data bus that exists with
common I/O devices. Each port is accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR II+ read and write ports are completely independent
of one another. To maximize data throughput, both read and write
ports are equipped with DDR interfaces. Each address location
is associated with four 8-bit words (CY7C1561KV18), 9-bit
words (CY7C1576KV18), or 36-bit words (CY7C1565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Selection Guide
Description
Maximum operating frequency
Maximum operating current
550 MHz
550
×8
900
×9
900
×36
1310
500 MHz
500
830
830
1210
450 MHz
450
760
760
1100
400 MHz
400
690
690
1000
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V_DDQ = 1.4 V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15878 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 10, 2011
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