CY7C1338F Datasheet, PDF (4/17 Pages) Cypress Semiconductor – 4-Mb (128K x 32) Flow-Through Sync SRAM

CY7C1338F
Pin Descriptions (continued)
Name
ADV
ADSP
ADSC
ZZ
DQs
V_DD
V_SS
V_DDQ
V_SSQ
MODE
NC
TQFP
BGA
I/O
Description
83
G4
Input- Advance Input signal, sampled on the rising edge of CLK. When
Synchronous asserted, it automatically increments the address in a burst cycle.
84
A4
Input- Address Strobe from Processor, sampled on the rising edge of CLK,
Synchronous active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A_[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when _{CE1 is deasserted HIGH}
85
B4
Input- Address Strobe from Controller, sampled on the rising edge of CLK,
Synchronous active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A_[1:0] are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
64
T7
Input- ZZ “sleep” Input, active HIGH. When asserted HIGH places the device
Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,
7,8,9,12,
13,18,19,
22,23,24,
25,28,29
K6,K7,L6,
I/O- Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
L7,M6,N6, Synchronous register that is triggered by the rising edge of CLK. As outputs, they deliver
N7,P7,D7,
the data contained in the memory location specified by the addresses
E6,E7,F6,
presented during the previous clock rise of the read cycle. The direction of
G6,G7,H6,
the pins is controlled by _OE. When _OE is asserted LOW, the pins behave
H7,D1,E1,
as outputs. When HIGH, DQs are placed in a three-state condition.
E2,F2,G1,
G2,H1,H2,
K1,K2,L1,
L2,M2,N1
N2,P1
15,41,65, C4,J2,J4,
91
R4,J6
Power Power supply inputs to the core of the device.
Supply
17,40,67,
90
D3,D5,E3,
E5,F3,F5,
H3,H5,K3,
K5,M3,M5,
N3,N5,P3,
P5
Ground
Ground for the core of the device.
4,11,20, A1,A7,F1,
27,54,61, F7,J1,J7,
70,77 M1,M7,U1,
U7
I/O Power
Supply
Power supply for the I/O circuitry.
5,10,21,55
–
,60,71,76
I/O Ground Ground for the I/O circuitry.
31
R3
Input- Selects Burst Order. When tied to GND selects linear burst sequence.
Static When tied to V_DD or left floating selects interleaved burst sequence. This
is a strap pin and should remain static during device operation. Mode Pin
has an internal pull-up.
14,16,38,
39,42,43,
66,51,80,
1,30
B1,B6,B7,
C1,C7,D4,
J3,J5,L4,
R1,R5,R7,
T1,T2,T6,
U2,U3,U4,
U5,U6,P6,
D6,D2,P2
No Connects. Not Internally connected to the die.
Document #: 38-05218 Rev. *A
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