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CY7C1338F Datasheet, PDF (3/17 Pages) Cypress Semiconductor – 4-Mb (128K x 32) Flow-Through Sync SRAM
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CY7C1338F
Pin Configurations (continued)
1
A
VDDQ
B
NC
C
NC
D
DQC
E
DQC
F
VDDQ
G
DQC
H
DQC
J
VDDQ
K
DQD
L
DQD
M
VDDQ
N
DQD
P
DQD
R
NC
T
NC
U
VDDQ
2
A
CE2
A
NC
DQC
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
NC
A
NC
NC
119-Ball BGA
3
A
A
A
VSS
VSS
VSS
BWC
VSS
NC
VSS
BWD
VSS
VSS
VSS
MODE
A
NC
4
ADSP
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
A
NC
5
A
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
BWA
VSS
VSS
VSS
NC
A
NC
6
A
NC
A
NC
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
NC
A
NC
NC
7
VDDQ
NC
NC
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
DQA
NC
ZZ
VDDQ
Pin Descriptions
Name
A0, A1, A
BWA,BWB
BWC,BWD
GW
BWE
CLK
CE1
CE2
CE3
OE
TQFP
BGA
I/O
Description
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,81,82,
99,100
P4,N4,A2, Input- Address Inputs used to select one of the 128K address locations.
A3,A5,A6, Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,
B3,B5,C2,
C3,C5,C6,
and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
R2,R6,T3,
T4,T5
93,94,95, L5,G5,G3, Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
96
L3 Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.
88
H4
Input- Global Write Enable Input, active LOW. When asserted LOW on the
Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW[A:D] and BWE).
87
M4
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of
Synchronous CLK. This signal must be asserted LOW to conduct a byte write.
89
K4
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during a
burst operation.
98
E4
Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP
is ignored if CE1 is HIGH.
97
B2
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE1 and CE3 to select/deselect the device.
92
-
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE1 and CE2 to select/deselect the device.
86
F4
Input- Output Enable, asynchronous input, active LOW. Controls the direction
Asynchronous of the I/O pins. When LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when emerging from a
deselected state.
Document #: 38-05218 Rev. *A
Page 3 of 17
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