CY7C1325H Datasheet, PDF (4/21 Pages) Cypress Semiconductor – 4-Mbit (256 K × 18) Flow-Through Sync SRAM

CY7C1325H
Pin Definitions
Name
A₀, A₁, A
BW_A,BW_B
GW
BWE
CLK
CE₁
CE₂
CE₃
OE
ADV
ADSP
ADSC
ZZ
DQs
DQP_A,
DQP_B
V_DD
V_SS
V_DDQ
MODE
NC
I/O
Description
Input- Address inputs used to select one of the 256 K address locations. Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃ are sampled active. A_[1:0] feed the 2
bit counter.
Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
synchronous Sampled on the rising edge of CLK.
Input-
synchronous
Input-
synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
is conducted (all bytes are written, regardless of the values on BW_[A:B] and BWE).
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
Input-clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE₂
synchronous and CE₃ to select/deselect the device. ADSP is ignored _{if CE1 is HIGH. CE1 is sampled only when a}
new external address is loaded.
Input-
synchronous
Input-
synchronous
Input-
asynchronou
s
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE₁
and CE₃ to select/deselect the device. CE₂ is sampled only when a new external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE₁
and CE₂ to select/deselect the device. CE₃ is sampled only when a new external address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input- Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically
synchronous increments the address in a burst cycle.
Input-
synchronous
Input-
synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A_[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when _CE1 is deasserted HIGH.
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A_[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input- ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronou condition with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ
s
pin has an internal pull-down.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP_[A:B] are placed in a tristate condition.
Power supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O power Power supply for the I/O circuitry.
supply
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to V_DD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
–
No connects. Not Internally connected to the die.
Document Number: 001-86114 Rev. **
Page 4 of 21