CY7C1297A Datasheet, PDF (4/13 Pages) Cypress Semiconductor – 64K X 18 Synchronous Burst SRAM

CY7C1297A/
GVT7164B18
Pin Descriptions (continued)
QFP Pins
Pin Name
Type
Description
86
OE
Input
Output Enable: This active LOW asynchronous input enables the data
output drivers.
83
ADV
Input- Address Advance: This active LOW input is used to control the internal
Synchronous burst counter. A HIGH on this pin generates wait cycle (no address
advance).
84
ADSP
Input- Address Status Processor: This active LOW input, along with CE being
Synchronous LOW, causes a new external address to be registered and a Read cycle is
initiated using the new address.
85
ADSC
Input- Address Status Controller: This active LOW input causes device to be
Synchronous deselected or selected along with new external address to be registered. A
Read or Write cycle is initiated depending upon Write control inputs.
31
MODE
Input- Mode: This input selects the burst sequence. A LOW on this pin selects
Static
Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
64
ZZ
Input- Snooze: This active HIGH input puts the device in low power consumption
Asynchronous standby mode. For normal operation, this input has to be either LOW or NC
(No Connect).
58, 59, 62, 63, 68, DQ1–DQ16
69, 72, 73, 8, 9, 12,
13, 18, 19, 22, 23
Input/
Output
Data Inputs/Outputs: Low Byte is DQ1–DQ8. High Byte is DQ9–DQ16.
Input data must meet set-up and hold times around the rising edge of CLK.
74, 24
DQP1,
DQP2
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity
bit for DQ9–DQ16.
15, 41, 65, 91
14, 17, 40, 67, 90
4, 11, 20, 27, 54, 61,
70, 77
V_CC
V_SS
V_CCQ
Supply
Ground
I/O Supply
Power Supply: +3.3V –5% and +10%
Ground: GND.
Output Buffer Supply: +2.375 to 3.6V
5, 10, 21, 26, 55, 60,
71, 76
V_SSQ
I/O Ground Output Buffer Ground: GND
1–3, 6, 7, 14, 16, 25,
NC
28–30, 38, 39, 42,
43, 49–53, 56, 57,
66, 75, 78, 79, 80,
95, 96
–
No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/V_CC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Document #: 38-05204 Rev. *A
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