CY62128E Datasheet, PDF (4/11 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM

CY62128E MoBL^®
Thermal Resistance^[9]
Parameter
Description
Test Conditions
Θ_JA Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,
(Junction to Ambient) two-layer printed circuit board
Θ_JC Thermal Resistance
(Junction to Case)
SOIC
Package
48.67
STSOP
Package
32.56
25.86
3.59
TSOP
Package
33.01
Unit
°C/W
3.42
°C/W
AC Test Loads and Waveforms
R1
V_CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
3.0V
10%
90%
90%
10%
R2
GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
R_TH
V
Parameters
Value
Unit
R1
1800
Ω
R2
990
Ω
R_TH
639
Ω
V_TH
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
V_DR
I_CCDR ^[8]
V_CC for Data Retention
Data Retention Current
t_CDR ^[9]
t_R ^[10]
Chip Deselect to Data
Retention Time
Operation Recovery
Time
Conditions
V_CC= V_DR, CE₁ > V_CC − 0.2V or CE₂ < 0.2V,
V_IN > V_CC - 0.2V or V_IN < 0.2V
Ind’l/Auto-A
Auto-E
Min Typ^[3] Max Unit
2
V
4 µA
30 µA
0
ns
t_RC
ns
Data Retention Waveform^[11]
V_CC
CE
V_CC(min)
t_CDR
DATA RETENTION MODE
V_DR > 2.0V
V_CC(min)
t_R
Notes
10. Full device AC operation requires linear V_CC ramp from V_DR to V_CC(min) > 100 µs or stable at V_CC(min) > 100 µs.
11. CE is the logical combination of CE₁ and CE₂. When CE₁ is LOW and CE₂ is HIGH, CE is LOW; when CE₁ is HIGH or CE₂ is LOW, CE is HIGH.
Document #: 38-05485 Rev. *E
Page 4 of 11
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