CY62128E Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM

CY62128E MoBL^®
1-Mbit (128K x 8) Static RAM
Features
• Very high speed: 45 ns
• Temperature ranges
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62128B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 4 µA (Industrial)
• Ultra low active power
— Typical active current: 1.3 mA @ f = 1 MHz
• Easy memory expansion with CE₁, CE₂ and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC,
and 32-pin TSOP I packages
Logic Block Diagram
Functional Description^[1]
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE₁ HIGH
or CE₂ LOW). The eight input and output pins (IO₀ through
IO₇) are placed in a high impedance state when the device is
deselected (CE₁ HIGH or CE₂ LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE₁ LOW and
CE₂ HIGH and WE LOW)
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO₀ through IO₇) is then written into the location
specified on the address pins (A₀ through A₁₆).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appears on
the IO pins.
INPUT BUFFER
IO0
A0
A1
IO1
A2
A3
IO2
A4
A5
128K x 8
IO3
A6
A7
ARRAY
IO4
A8
A9
IO5
A10
A11
IO6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05485 Rev. *E
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 07, 2007
[+] Feedback