CY29351 Datasheet, PDF (4/8 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer

CY29351
DC Electrical Specifications (V_DD = 3.3V ± 5%, T_A = –40°C to +85°C) (continued)
Parameter
I_IL
I_IH
I_DDA
I_DDQ
I_DD
Description
Input Current, Low^[6]
Input Current, High^[6]
PLL Supply Current
Quiescent Supply Current
Dynamic Supply Current
Condition
Min.
Typ.
Max.
Unit
V_IL = V_SS
V_IL = V_DD
AVDD only
–
–
–100
µA
–
–
100
µA
–
5
10
mA
All VDD pins except AVDD
–
–
7
mA
Outputs loaded @ 100 MHz
–
270
–
mA
Outputs loaded @ 200 MHz
–
300
–
C_IN
Input Pin Capacitance
–
4
–
pF
Z_OUT
Output Impedance
12
15
18
Ω
AC Electrical Specifications (V_DD = 2.5V ± 5%, T_A = –40°C to +85°C) ^[7]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
f_VCO
f_in
VCO Frequency
Input Frequency
÷2 Feedback
÷4 Feedback
200
–
100
–
50
–
380
MHz
190
MHz
95
÷8 Feedback
25
–
47.5
Bypass mode (PLL_EN = 0)
0
–
200
f_refDC
V_PP
V_CMR
t_r , t_f
f_MAX
Input Duty Cycle
Peak-Peak Input Voltage
Common Mode Range^[8]
TCLK Input Rise/FallTime
Maximum Output Frequency
LVPECL
LVPECL
0.7V to 1.7V
÷2 Output
÷4 Output
25
–
75
%
500
–
1000
mV
1.2
–
V_DD – 0.6
V
–
–
1.0
ns
100
–
190
MHz
50
–
95
÷8 Output
25
–
47.5
DC
Output Duty Cycle
f_MAX < 100 MHz
f_MAX > 100 MHz
t_r , t_f
Output Rise/Fall times
0.6V to 1.8V
t_(φ)
Propagation Delay (static phase TCLK to FB_IN
offset)
PCLK to FB_IN
47.5
–
52.5
%
45
–
55
0.1
–
1.0
ns
–100
–
100
ps
–100
–
100
t_sk(O)
t_{PLZ, HZ}
t_{PZL, ZH}
BW
Output-to-Output Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
(–3dB)
÷2 Feedback
÷4 Feedback
–
–
150
ps
–
–
10
ns
–
–
10
ns
–
2.2
–
MHz
–
0.85
–
÷8 Feedback
–
0.6
–
t_JIT(CC)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
–
–
150
ps
–
–
250
t_JIT(PER)
Period Jitter
Same frequency
Multiple frequencies
–
–
100
ps
–
–
175
t_JIT(φ)
I/O Phase Jitter
–
175
–
ps
t_LOCK
Maximum PLL Lock Time
–
–
1
ms
Notes:
7. AC characteristics apply for parallel output termination of 50Ω to V_TT. Parameters are guaranteed by characterization and are not 100% tested.
8. V_CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V_CMR range and the input swing
lies within the V_PP (AC) specification. Violation of V_CMR or V_PP impacts static phase offset t(φ).
Document #: 38-07475 Rev. *A
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