CY29351 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer

CY29351
2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
Features
• Output frequency range: 25 MHz to 200 MHz
• Input frequency range: 25 MHz to 200 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2.5% max Output duty cycle variation
• 9 Clock outputs: Drive up to 18 clock lines
• Two reference clock inputs: LVPECL or LVCMOS
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9351
• Industrial temperature range: –40°C to +85°C
• 32-Pin 1.0-mm TQFP package
Block Diagram
Functional Description
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2,
and 5 outputs. Bank A divides the VCO output by 2 or 4 while
the other banks divide by 4 or 8 per SEL(A:D) settings, see
Functional Table. These dividers allow output to input ratios of
4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output
can drive 50Ω series or parallel terminated transmission lines.
For series terminated transmission lines, each output can
drive one or two traces giving the device an effective fanout of
1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see the
Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
SELA
PLL_EN
REF_SEL
TCLK
PECL_CLK
FB_IN
SELB
SELC
OE#
SELD
Phase
Detector
VCO
200 -
500 MHz
LPF
÷2 / ÷4
÷4 / ÷8
÷4 / ÷8
÷4 / ÷8
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
AVDD
FB_IN
SELA
SELB
SELC
SELD
AVSS
PECL_CLK
1
24 QC0
2
23 VDDQC
3
22 QC1
4
5
CY29351
21
20
VSS
QD0
6
19 VDDQD
7
18 QD1
8
17 VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07475 Rev. *A
Revised July 26, 2004