CY2300_12 Datasheet, PDF(4/9 Page) Cypress Semiconductor

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CY2300_12 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – Phase-Aligned Clock Multiplier

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Switching Waveforms (continued)

Figure 3. All Outputs Rise/Fall Time

2.0V

OUTPUT 0.8V

2.0V

0.8V

3.3V

Figure 4. Output to Output Skew

OUTPUT

VDD/2

OUTPUT

VDD/2

Figure 5. Input to Output Propagation Delay

REFIN

VDD/2

OUTPUT

VDD/2

Figure 6. Device to Device Skew

1/2xREF, Device1

VDD/2

1/2xREF, Device2

VDD/2

Test Circuits

0.1 ïF

Figure 7. Test Circuit #1

VDD

OUTPUTS

CLK OUT

C LOAD

GND

Document #: 38-07252 Rev. *D

CY2300

Page 4 of 9

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