CY2300_12 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – Phase-Aligned Clock Multiplier

CY2300
Phase-Aligned Clock Multiplier
Phase-Aligned Clock Multiplier
Features
■ 4-multiplier configuration
■ Single PLL architecture
■ Phase alignment
■ Low jitter, high accuracy outputs
■ Output enable pin
■ 3.3 V operation
■ 5 V tolerant input
■ Internal loop filter
■ 8-pin 150-mil small-outline integrated circuit (SOIC) package
■ Commercial temperature
Functional Description
The CY2300 is a 4 output 3.3 V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN
output frequencies on respective output pins.
The part has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The input-to-output skew is
guaranteed to be less than 200 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
Multiple CY2300 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
The CY2300 is available in commercial temperature range.
Logic Block Diagram
FBK
REFIN
/2
PLL
OE
Divider
Logic
1/2xREF
REF
REF
2xREF
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07252 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 01, 2010
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