CY2213 Datasheet, PDF (4/10 Pages) Cypress Semiconductor – High-Frequency Programmable PECL Clock Generator

CY2213
PLL Frequency = Reference x P/Q = Output
Reference
Q
Φ
VCO
Absolute Maximum Conditions
P
PLL
Figure 4. PLL Block Diagram
The following table reflects stress ratings only, and functional
operation at the maximums are not guaranteed.
Parameter
V_DD,ABS
V_{I, ABS}
Description
Max. voltage on V_DD, or V_DDX with respect to ground
Max. voltage on any pin with respect to ground
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External
capacitors are required in the crystal oscillator circuit. Please
refer to the application note entitled Crystal Oscillator Topics
for details.
Parameter
X_F
Frequency
DC Electrical Specifications
Description
Parameter
V_DD
T_A
V_IL
V_IH
R_PUP
t_PU
Description
Supply voltage
Ambient operating temperature
Input signal low voltage at pin S
Input signal high voltage at pin S
Internal pull-up resistance
Power-up time for all V_DDs to reach minimum specified voltage
(power ramps must be monotonic)
AC Electrical Specifications
Parameter
f_IN
f_XTAL,IN
C_IN,CMOS
Description
Input frequency with driven reference
Input frequency with crystal input
Input capacitance at S pin^[1]
3.3V DC Device Characteristics (Driving load, Figure 5)
Parameter
Description
V_OH
Output high voltage, referenced to V_DD
V_OL
Output low voltage, referenced to V_DD
3.3V DC Device Characteristics (Driving load, Figure 6)
Parameter
Description
V_OH
Output high voltage
V_OL
Output low voltage
Note:
1. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
Output
Min.
–0.5
–0.5
Max.
4.0
V_DD+0.5
Unit
V
V
Min.
10
Min.
3.00
0
0.65
10
0.05
Max.
31.25
Max.
3.60
70
0.35
100
500
Unit
MHz
Unit
V
°C
V_DD
V_DD
kΩ
ms
Min.
1
10
Max.
133
31.25
10
Unit
MHz
MHz
pF
Min.
Typ.
Max.
Unit
–1.02
–0.95
–0.88
V
–1.81
–1.70
–1.62
V
Min.
1.1
0
Typ.
1.2
0
Max.
Unit
1.3
V
0
V
Document #: 38-07263 Rev. *E
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