CY14B104K Datasheet, PDF (4/33 Pages) Cypress Semiconductor – 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

CY14B104K, CY14B104M
Table 1. Pin Definitions (continued)
Pin Name
INT
V_SS
V_CC
HSB
V_CAP
I/O Type
Description
Output
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground Ground for the device. Must be connected to ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output
Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (t_HHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
The CY14B104K/CY14B104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B104K/CY14B104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See the Truth Table For SRAM Operations on page
25 for a complete description of read and write modes.
SRAM Read
The CY14B104K/CY14B104M performs a read cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A_0-18 or A_0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t_AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t_ACE or at t_DOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t_AA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DO_0-15
are written into the memory if it is valid t_SD before the end of a
WE controlled write or before the end of an CE controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. It is recommended that OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers t_HZWE after WE goes LOW.
AutoStore Operation
The CY14B104K/CY14B104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device
power-down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104K/CY14B104M.
During a normal operation, the device draws current from V_CC to
charge a capacitor connected to the V_CAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V_CC pin drops below V_SWITCH, the part
automatically disconnects the V_CAP pin from V_CC. A STORE
operation is initiated with power provided by the V_CAP capacitor.
Note If the capacitor is not connected to V_CAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. In case AutoStore is enabled without a
capacitor on V_CAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2. AutoStore Mode
V_CC
0.1 uF
V_CC
WE
V_CAP
V_SS
V_CAP
Document #: 001-07103 Rev. *S
Page 4 of 33
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