CY14B104K Datasheet, PDF (3/33 Pages) Cypress Semiconductor – 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

CY14B104K, CY14B104M
Pinouts
Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II
INT
NC ^[5]
1
2
44
43
A₀ 3
42
A_{1 4}
41
A_{2 5}
40
A₃ 6
39
A₄ 7
38
CE 8
37
DQ₀ 9 44 - TSOP II ₃₆
DQ₁ 10
(x8)
35
V_CC
V_SS
DQ₂
11
12
13
Top View
(not to scale)
34
33
32
DQ₃ 14
31
WE 15
30
A₅ 16
29
A₆ 17
28
A₇ 18
27
A_{8 19}
26
A_{9 20}
25
X_{out 21}
24
X_{in 22}
23
HSB
NC_[4]
NC
A₁₈
A₁₇
A₁₆
A₁₅
OE
DQ₇
DQ₆
V_SS
V_CC
DQ5
DQ4
V_CAP
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
V_RTCcap
V_RTCbat
NICN^[T5]
1
2
54
53
A_{0 3}
52
A_{1 4}
51
A_{2 5}
50
A_{3 6}
49
A_{4 7}
48
CE 8
47
DQ_{0 9}
46
DQ₁ 10 54 - TSOP II 45
DQ₂
DQ₃
V_CC
V_SS
11
(x16)
44
12
43
13 _{Top View} ⁴²
14 (not to scale) ⁴¹
DQ_{4 15}
40
DQ_{5 16}
39
DQ₆ 17
38
DQ₇ 18
WE ₁₉
A_{5 20}
37
36
35
A_{6 21}
34
A₇ 22
33
A₈ 23
32
A₉ 24
X^N_ou^C_t
25
26
31
30
29
X_in 27
28
HNSCB_[4]
A₁₇
A₁₆
A₁₅
OE
BHE
BLE
DQ₁₅
DQ₁₄
DQ₁₃
DQ₁₂
V_SS
V_CC
DQ₁₁
DQ₁₀
DQ₉
DQ₈
V_CAP
A₁₄
A₁₃
A₁₂
A₁₁
A₁₀
NC
V_RTCcap
V_RTCbat
Table 1. Pin Definitions
Pin Name I/O Type
Description
A₀ – A₁₈
A₀ – A₁₇
DQ₀ – DQ₇
DQ₀ – DQ₁₅
NC
Input
Input/Output
No connect
Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for x8 configuration.
Address inputs. Used to select one of the 262,144 words of the nvSRAM for x16 configuration.
Bidirectional data I/O lines for ×8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O lines for ×16 configuration. Used as input or output lines depending on operation.
No connects. This pin is not connected to the die.
WE
Input
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
Input
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
BHE
BLE
X_out
X_in
V_RTCcap
V_RTCbat
Input
Input
Output
Byte High Enable, Active LOW. Controls DQ₁₅ - DQ₈.
Byte Low Enable, Active LOW. Controls DQ₇ - DQ₀.
Crystal connection. Drives crystal on startup.
Input
Crystal connection. For 32.768 kHz crystal.
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if V_RTCbat is used.
Power supply Battery supplied backup RTC supply voltage. Left unconnected if V_RTCcap is used.
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-07103 Rev. *S
Page 3 of 33
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