C9531 Datasheet, PDF (4/10 Pages) Cypress Semiconductor – PCIX I/O System Clock Generator with EMI Control Features

C9531
Byte 0: Output Register (continued)
2
0
1
0
0
1
HWSEL
Not used
Not used
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
0
0
Byte0, bit5
0
1
Description
Frequency generated from second PLL
Frequency generated from XIN
1
0
Spread @ –1.0%
1
1
Spread @ –0.5%
Table 5. Test Table
Test Function Clock
Frequency
CLK
XIN/4
Outputs
REF
XIN
Note
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte 1: CPU Register
Bit
@Pup
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Name
REFEN
Reserved
Reserved
REF Output Enable
0 = Disable, 1= Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 2: PCI Register
Bit
@Pup
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Name
18
19
22
23
24
Reserved
Reserved
Reserved
CLK4 Output Enable
0 = Disable, 1= Enable
CLK3 Output Enable
0 = Disable, 1= Enable
CLK2Output Enable
0 = Disable, 1= Enable
CLK1 Output Enable
0 = Disable, 1= Enable
CLK0 Output Enable
0 = Disable, 1= Enable
Description
Document #: 38-07034 Rev. *D
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