C9531 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – PCIX I/O System Clock Generator with EMI Control Features

C9531
PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of 5 clocks.
• One REF XIN clock output.
• SMBus clock control interface for individual clock
disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pin for entire output bank enable control and
testability
• 28-pin SSOP and TSSOP packages
Block Diagram
Table 1. Test Mode Logic Table^[1]
OE
HIGH
HIGH
HIGH
HIGH
LOW
Input Pins
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLK
REF
XIN
XIN
2 * XIN
XIN
3 * XIN
XIN
4 * XIN
XIN
Three-state Three-state
Pin Configuration
SSCG#
SSCG
Logic
XIN
XOUT
/N ₁
0
SDATA
SCLK
IA(0:2)
S(0,1)
I²C
Control
Logic
CLK0
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
Note:
1. XIN is the frequency of the clock on the device’s XIN pin.
REF 1
VDD 2
XIN 3
XOUT 4
VSS 5
S0 6
S1 7
GOOD# 8
VSS 9
IA0 10
IA1 11
IA2 12
VDDA 13
OE 14
28 _SDATA
27 _SCLK
26 _VSS
25 _VDDP
24 CLK0
23 CLK1
22 CLK2
21 ^VSS
20 VDDP
19 CLK3
18 CLK4
17 _VDDA
16 _VSS
15 _SSCG#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07034 Rev. *D
Revised May 12, 2003