CY8C24633_12 Datasheet, PDF (39/52 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip

CY8C24633
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  T_A  85 °C, or 3.0 V to 3.6 V and –40 °C  T_A  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 32. AC Programming Specifications
Symbol
T_RSCLK
T_FSCLK
T_SSCLK
T_HSCLK
F_SCLK
T_ERASEB
T_WRITE
T_DSCLK
T_DSCLK3
T_ERASEALL
Description
Rise time of SCLK
Fall time of SCLK
Data set up time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (Block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Flash erase time (Bulk)
T_{PROGRAM_HOT} Flash block erase + flash block write time
T_{PROGRAM_COLD} Flash block erase + flash block write time
Min Typ Max Units
Notes
1
–
20
ns
1
–
20
ns
40
–
–
ns
40
–
–
ns
0
–
8
MHz
–
20
–
ms
–
80
–
ms
–
–
45
ns V_dd  3.6
–
–
50
ns 3.0  V_dd  3.6
–
20
– ms
Erase all blocks and
protection fields at once.
–
–
200 ms
0 °C  T_J  100 ° C
–
–
400 ms
–40 °C  T_J  0 °C
SAR8 ADC AC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  T_A  85 °C, or 3.0 V to 3.6 V and –40 °C  T_A  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 33. SAR8 ADC AC Specifications
Symbol
Freq₃
Freq₅
Description
Input clock frequency 3 V
Input clock frequency 5 V
Min Typ Max Units
–
–
3.0 MHz
–
–
3.0 MHz
Notes
Notes
20. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
21. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 001-20160 Rev. *G
Page 39 of 52