CY8C24633_12 Datasheet, PDF (31/52 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip

PLL
Enable
F_PLL
PLL
Gain ⁰
Figure 6. PLL Lock Timing Diagram
T_PLLSLEW
24 MHz
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
F_PLL
T_PLLSLEWLOW
24 MHz
PLL
Gain ¹
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
T_OS
F_32K2
32 kHz
CY8C24633
Document Number: 001-20160 Rev. *G
Page 31 of 52