CY8CLED16_1106 Datasheet, PDF (38/53 Pages) Cypress Semiconductor – EZ-Color HB LED Controller Visual embedded design Binning compensation

CY8CLED16
Table 27. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
Min Typ Max Units
T_ROB
Rising Settling Time to 0.1%, 1 V Step, 100pF
Load
–
Power = Low
–
Power = High
–
4.7
s
–
4.7
s
T_SOB
Falling Settling Time to 0.1%, 1 V Step, 100pF
Load
–
–
4
s
Power = Low
–
–
4
s
Power = High
SR_ROB
Rising Slew Rate (20% to 80%), 1 V Step,
100pF Load
Power = Low
Power = High
.36
–
.36
–
–
V/s
–
V/s
SR_FOB
Falling Slew Rate (80% to 20%), 1 V Step,
100pF Load
Power = Low
Power = High
.4
–
.4
–
–
V/s
–
V/s
BW_OB Small Signal Bandwidth, 20mV_pp, 3dB BW,
100pF Load
0.7
–
Power = Low
0.7
–
Power = High
–
MHz
–
MHz
BW_OB
Large Signal Bandwidth, 1V_pp, 3dB BW,
100pF Load
Power = Low
Power = High
200
–
200
–
–
kHz
–
kHz
Notes
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and -40 °C  T_A  85 °C, or 3.0 V to 3.6 V and -40 °C  T_A  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 28. 5V AC External Clock Specifications
Symbol
F_OSCEXT
–
–
–
Description
Frequency
High Period
Low Period
Power Up IMO to Switch
Min Typ Max Units
0.093 –
24.6 MHz
20.6
–
5300 ns
20.6
–
–
ns
150
–
–
s
Notes
Table 29. 3.3V AC External Clock Specifications
Symbol
Description
Min Typ Max Units
Notes
F_OSCEXT Frequency with CPU Clock Divide 0.093
–
by 1
12.3 MHz Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the
external clock must adhere to the maximum
frequency and duty cycle requirements.
F_OSCEXT Frequency with CPU Clock Divide 0.186
–
by 2 or Greater
24.6 MHz If the frequency of the external clock is greater
than 12 MHz, the CPU clock divider must be
set to 2 or greater. In this case, the CPU clock
divider will ensure that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock Divide 41.7
–
5300 ns
–
by 1
–
Low Period with CPU Clock Divide 41.7
–
–
ns
–
by 1
–
Power Up IMO to Switch
150
–
–
s
–
Document Number: 001-13105 Rev. *H
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