CY7C63743-SXC Datasheet, PDF(37/49 Page) Cypress Semiconductor – enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller

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CY7C63743-SXC Datasheet, PDF (37/49 Pages) Cypress Semiconductor – enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller

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FOR

CY7C63722

FOR

CY7C63723

CY7C63743

23.0 Register Summary

Address

0x00 Port 0 Data

0x01 Port 1 Data

0x02 Port 2 Data

0x0A

0x0B

0x0C

0x0D

0x04

0x05

0x06

0x07

GPIO Port 0 Mode 0

GPIO Port 0 Mode 1

GPIO Port 1 Mode 0

GPIO Port 1 Mode 1

Port 0 Interrupt Enable

Port 1 Interrupt Enable

Port 0 Interrupt Polarity

Port 1 Interrupt Polarity

Bit 7

Bit 6

Reserved

Bit 5

D+(SCLK)

State

Bit 4

Bit 3

Bit 2

D- (SDATA)

State

Reserved

P0[7:0] Mode0

P0[7:0] Mode1

P1[7:0] Mode0

P1[7:0] Mode1

P0[7:0] Interrupt Enable

P1[7:0] Interrupt Enable

P0[7:0] Interrupt Polarity

P1[7:0] Interrupt Polarity

Bit 1

P2.1 (Int Clk

Mode Only

Bit 0

VREG Pin

State

Read/Write/

Both/

BBBBBBBB

--RR--RR

Default/

Reset

00000000

WWWWWWWW 00000000

0xF8 Clock Configuration

Ext. Clock

Resume

Delay

Wake-up Timer Adjust Bit [2:0]

Low-voltage

Reset

Disable

Precision

USB

Clocking

Enable

Internal

Clock

Output

Disable

External

Oscillator

Enable

BBBBBBBB 00000000

0x10 USB Device Address

0x12 EP0 Mode

0x14, EP1, EP2 Mode Register

0x16

0x11, EP0,1, and 2 Counter

0x13, and

0x15

Device

Address

Enable

SETUP

Received

STALL

Data 0/1

Toggle

Device Address

Received

OUT

ACKed

Received Transaction

Reserved

ACKed

Transaction

Data Valid

Reserved

Mode Bit

Byte Count

BBBBBBBB 00000000

B--BBBBB 00000000

BB--BBBB 00000000

0x1F USB Status and Control PS/2 Pull-up

Enable

VREG

Enable

USB

Reset-PS/2

Activity

Interrupt

Mode

Reserved

USB Bus

Activity

D+/D- Forcing Bit

BBB-BBBB 00000000

0x20 Global Interrupt Enable

Wake-up

Interrupt

Enable

0x21 Endpoint Interrupt Enable

GPIO

Interrupt

Enable

Capture

Timer B Intr. Timer A Intr.

Enable

SPI

Interrupt

Enable

Reserved

1.024 ms

Interrupt

Enable

EP2

Interrupt

Enable

128 Âµs

Interrupt

Enable

EP1

Interrupt

Enable

USB Bus

Reset-PS/2

Activity Intr.

Enable

EP0

Interrupt

Enable

BBBBBBBB

-----BBB

00000000

0x24

0x25

Timer LSB

Timer (MSB)

Reserved

Timer Bit [7:0]

Timer Bit [11:8]

RRRRRRRR

----RRRR

00000000

0x60

0x61

SPI Data

SPI Control

TCMP

TBF

Data I/O

Comm Mode [1:0]

CPOL

CPHA

SCK Select

BBBBBBBB

00000000

0x40

0x41

0x42

0x43

0x44

0x45

0xFF

Capture Timer A-Rising,

Data Register

Capture Timer A-Falling,

Data Register

Capture Timer B-Rising,

Data Register

Capture Timer B-Falling,

Data Register

Capture Timer

Configuration

Capture Timer Status

Process Status & Control

First Edge

Hold

IRQ

Pending

Capture A Rising Data

Capture A Falling Data

Capture B Rising Data

Capture B Falling Data

Prescale Bit [2:0]

Reserved

Watch Dog

Reset

Bus

Interrupt

Event

LVR/BOR

Reset

Capture B

Falling Intr

Enable

Capture B

Rising Intr

Enable

Capture A

Falling Intr

Enable

Capture A

Rising Intr

Enable

Capture B Capture B Capture A Capture A

Falling Rising Event Falling Rising Event

Event

Suspend Interrupt Reserved

Run

Enable

Sense

RRRRRRRR

BBBBBBBB

----BBBB

RBBBBR-B

00000000

See

Section

20.0

Document #: 38-08022 Rev. *B

Page 37 of 49

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