CYW20734 Datasheet, PDF (36/51 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver for Wireless Input Devices

CYW20734
3.3.3 BSC Interface Timing
The specifications in Table 22 references Figure 12.
Table 22. BSC Interface Timing Specifications (up to 1 MHz)
Reference
1
Clock frequency
Characteristics
2
START condition setup time
3
START condition hold time
4
Clock low time
5
Clock high time
6
Data input hold time^a
7
Data input setup time
8
STOP condition setup time
9
Output valid from clock
10
Bus free time^b
Minimum Maximum
Unit
100
–
400
800
kHz
1000
650
–
ns
280
–
ns
650
–
ns
280
–
ns
0
–
ns
100
–
ns
280
–
ns
–
400
ns
650
–
ns
a. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
b. Time that the CBUS must be free before a new transaction can start.
Figure 12. BSC Interface Timing Diagram
1
5
SCL
2
SDA
IN
SDA
OUT
4
3
6
7
9
8
10
Document Number: 002-14874 Rev. *S
Page 36 of 51