CY8C21234_07 Datasheet, PDF (36/42 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C21x34 Final Data Sheet
4.2 Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
Typical θ_JA *
Typical θ_JC
16 SOIC
123 ^oC/W
55 ^oC/W
20 SSOP
117 ^oC/W
41 ^oC/W
28 SSOP
96 ^oC/W
39 ^oC/W
32 QFN** 5x5 mm 0.60 MAX
27 ^oC/W
15 ^oC/W
32 QFN** 5x5 mm 0.93 MAX
22 ^oC/W
12 ^oC/W
* T_J = T_A + Power x θ_JA
** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the
PCB ground plane.
4.3 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-2. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature*
Maximum Peak Temperature
16 SOIC
240^oC
260^oC
20 SSOP
240^oC
260^oC
28 SSOP
240^oC
260^oC
32 QFN
240^oC
260^oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5^oC
with Sn-Pb or 245 ± 5^oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
4. Packaging Information
January 12, 2007
Document No. 38-12025 Rev. *K
36
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