CY14C512PA_12 Datasheet, PDF (35/42 Pages) Cypress Semiconductor – 512-Kbit (64 K × 8) SPI nvSRAM with Real Time Clock

CY14C512PA
CY14B512PA
CY14E512PA
AutoStore or Power-Up RECALL
Over the Operating Range
Parameter
Description
t_FA ^[19]
Power-Up RECALL duration
CY14C512PA
CY14B512PA
CY14E512PA
t_STORE ^[20]
t_DELAY ^[21]
V_SWITCH
STORE cycle duration
Time allowed to complete SRAM write cycle
Low voltage trigger level
CY14C512PA
CY14B512PA
CY14E512PA
t_VCCRISE[22]
V_HDIS[22]
t_LZHSB[22]
t_HHHD[22]
t_WAKE
V_CC rise time
HSB output disable voltage
HSB high to nvSRAM active time
HSB HIGH active time
Time for nvSRAM to wake up from SLEEP mode
CY14C512PA
CY14B512PA
CY14E512PA
t_SLEEP
t_SB ^[22]
Time to enter into SLEEP mode after Issuing SLEEP instruction
Time to enter into standby mode after CS going HIGH
Switching Waveforms
Figure 36. AutoStore or Power-Up RECALL ^[23]
V_CC
V_SWITCH
V_HDIS
CY14X512PA
Min
Max
–
40
–
20
–
20
–
8
–
25
–
2.35
–
2.65
–
4.40
150
–
–
1.9
–
5
–
500
–
40
–
20
–
20
–
8
–
100
Unit
ms
ms
ms
ms
ns
V
V
V
µs
V
µs
ns
ms
ms
ms
ms
µs
HSB OUT
t_VCCRISE
23
Note
t_HHHD
20
Note
t_STORE
t_HHHD
20
Note
t_STORE
23
Note
t_DELAY
AutoStore
t_LZHSB
t_LZHSB
POWER-
UP
RECALL
t_DELAY
t_FA
t_FA
Read & Write
Inhibited
(RWI)
POWER-UP Read & Write BROWN POWER-UP
Read & Write
RECALL
OUT
RECALL
AutoStore
Notes
19. t_FA starts from the time V_CC rises above V_SWITCH.
20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
21. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t_DELAY.
22. These parameters are guaranteed by design and are not tested.
23. Read and Write cycles are ignored during STORE, RECALL, and while V_CC is below V_SWITCH.
24. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
POWER
DOWN
AutoStore
Document Number: 001-65268 Rev. *D
Page 35 of 42