CY14C101PA_13 Datasheet, PDF (35/43 Pages) Cypress Semiconductor – 1-Mbit (128 K x 8) Serial (SPI) nvSRAM with Real Time Clock

CY14C101PA
CY14B101PA
CY14E101PA
AutoStore or Power-Up RECALL
Over the Operating Range
Parameter
Description
t_FA ^[20]
t_STORE ^[21]
t_DELAY ^[22]
V_SWITCH
t_VCCRISE[23]
V_HDIS[23]
t_LZHSB[23]
t_HHHD[23]
t_WAKE
t_SLEEP
t_SB[23]
Power-up RECALL duration
STORE cycle duration
Time allowed to complete SRAM write cycle
Low voltage trigger level
V_CC rise time
HSB output disable voltage
HSB high to nvSRAM active time
HSB HIGH active time
Time for nvSRAM to wake up from SLEEP mode
Time to enter into SLEEP mode after Issuing SLEEP instruction
Time to enter into standby mode after CS going HIGH
CY14C101PA
CY14B101PA
CY14E101PA
CY14C101PA
CY14B101PA
CY14E101PA
CY14C101PA
CY14B101PA
CY14E101PA
Switching Waveforms
V_CC
V_SWITCH
V_HDIS
Figure 36. AutoStore or Power Up RECALL ^[24]
CY14X101PA
Min
Max
–
40
–
20
–
20
–
8
–
25
–
2.35
–
2.65
–
4.40
150
–
–
1.9
–
5
–
500
–
40
–
20
–
20
–
8
–
100
Unit
ms
ms
ms
ms
ns
V
V
V
µs
V
µs
ns
ms
ms
ms
ms
µs
HSB OUT
t_VCCRISE
25
Note
t_HHHD
Note²¹
t_STORE
t_HHHD
Note²¹ t_STORE
25
Note
t_DELAY
AutoStore
t_LZHSB
t_LZHSB
POWER-
UP
RECALL
t_DELAY
t_FA
t_FA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN POWER-UP
OUT
RECALL
AutoStore
Read & Write
Notes
20. t_FA starts from the time V_CC rises above V_SWITCH.
21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
22. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t_DELAY.
23. These parameters are guaranteed by design and are not tested.
24. Read and Write cycles are ignored during STORE, RECALL, and while V_CC is below V_SWITCH.
25. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
POWER
DOWN
AutoStore
Document Number: 001-54392 Rev. *L
Page 35 of 43