BCM20705 Datasheet, PDF (35/67 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver and Baseband Processor

BCM20705 Data Sheet
SPI
SPI
The BCM20705 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock
rates may be possible. The physical interface between the SPI master and the BCM20705 consists of the four
SPI signals (SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO) and one interrupt signal (SPI_INT). The BCM20705
can be configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be
configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and
SPI_SO data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode,
half-duplex handshaking is implemented between the SPI master and the BCM20705.
SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the
middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop
the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented
in higher layer protocols.
Simultaneous UART Transport and Bridging
The BCM20705 supports UART or USB interfaces that can function as the host controller interface (HCI).
Typically, a customer application would choose one of the two interfaces and the other would be idle. The
BCM20705 allows the UART transport to operate simultaneously with the USB. To operate this way, the
assumption is that the USB would function as the primary host transport, while the UART would function as a
secondary communication channel that can operate at the same time. This can enable the following
applications:
• Bridging primary HCI transport traffic to another device via the UART
• Generic communication to an external device for a vendor-supported application via the UART
Simultaneous UART transport and bridging is enabled by including:
• Two dedicated 64-byte FIFOs, one for the input and one for the output
• Additional DMA channels
• Additional vendor-supported commands over the HCI transport
Broadcom®
Bluetooth Transceiver and Baseband Processor
November 13, 2014 • MCS20705-DS104-R
Page 34
BROADCOM CONFIDENTIAL