CY8C24123 Datasheet, PDF (34/41 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C24x23 Final Data Sheet
3. Electrical Specifications
3.4.8 AC I²C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-26. AC Characteristics of the I²C SDA and SCL Pins
Symbol
F_SCLI2C
T_HDSTAI2C
T_LOWI2C
T_HIGHI2C
T_SUSTAI2C
T_HDDATI2C
T_SUDATI2C
T_SUSTOI2C
T_BUFI2C
T_SPI2C
Description
SCL Clock Frequency
Standard Mode
Min
Max
0
100
Hold Time (repeated) START Condition. After this
4.0
–
period, the first clock pulse is generated.
LOW Period of the SCL Clock
4.7
–
HIGH Period of the SCL Clock
4.0
–
Set-up Time for a Repeated START Condition
4.7
–
Data Hold Time
0
–
Data Set-up Time
250
–
Set-up Time for STOP Condition
4.0
–
Bus Free Time Between a STOP and START Condition 4.7
–
Pulse Width of spikes are suppressed by the input fil- –
–
ter.
Fast Mode
Min
0
Max
400
0.6
–
1.3
–
0.6
–
0.6
–
0
–
100^a
–
0.6
–
1.3
–
0
50
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t_SU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t_rmax + t_SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA
T_LOWI2C
T_SUDATI2C
T_HDSTAI2C
T_SPI2C
T_BUFI2C
SCL
S ^T_HDSTAI2C ^THDDATI2C ^T_HIGHI2C
T_SUSTAI2C
Sr
T_SUSTOI2C
P
S
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I²C Bus
June 4, 2004
Document No. 38-12011 Rev. *F
34