CY8C24123 Datasheet, PDF (33/41 Pages) Cypress Semiconductor – PSoC Mixed Signal Array

CY8C24x23 Final Data Sheet
3. Electrical Specifications
3.4.6 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-23. 5V AC External Clock Specifications
Symbol
F_OSCEXT
–
–
–
Frequency
Description
High Period
Low Period
Power Up IMO to Switch
Min
0
20.6
20.6
150
Typ
–
–
–
–
Max
24.24
–
–
–
Units
MHz
ns
ns
µs
Notes
Table 3-24. 3.3V AC External Clock Specifications
Symbol
F_OSCEXT
F_OSCEXT
–
–
–
Description
Frequency with CPU Clock divide by 1^a
Frequency with CPU Clock divide by 2 or greater^b
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
Min
0
0
41.7
41.7
150
Typ
–
–
–
–
–
Max
12.12
24.24
–
–
–
Units
MHz
MHz
ns
ns
µs
Notes
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
3.4.7 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 3-25. AC Programming Specifications
Symbol
T_RSCLK
T_FSCLK
T_SSCLK
T_HSCLK
F_SCLK
T_ERASEB
T_WRITE
T_DSCLK
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Min
1
1
40
40
0
–
–
–
Typ
–
–
–
–
–
15
30
–
Max
20
20
–
–
8
–
–
45
Units
ns
ns
ns
ns
MHz
ms
ms
ns
Notes
June 4, 2004
Document No. 38-12011 Rev. *F
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