CY7C68013A_0905 Datasheet, PDF (34/62 Pages) Cypress Semiconductor – EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 12. FX2LP Register Summary (continued)
Hex Size Name
Description
xxxx
I²C Configuration Byte
b7
b6
0
DISCON
80 1
81 1
82 1
83 1
84 1
85 1
86 1
87 1
88 1
89 1
8A 1
8B 1
8C 1
8D 1
8E 1
8F 1
90 1
91 1
92 1
93 5
98 1
99 1
9A 1
9B 1
9C 1
9D 1
9E 1
9F 1
A0 1
A1 1
A2 1
A3 5
A8 1
A9 1
AA 1
AB 1
AC 1
AD 2
AF 1
B0 1
B1 1
B2 1
B3 1
B4 1
B5 1
B6 1
B7 1
B8 1
B9 1
BA 1
Special Function Registers (SFRs)
IOA^[13]
Port A (bit addressable) D7
SP
Stack Pointer
D7
DPL0
Data Pointer 0 L
A7
DPH0
DPL1^[13]
DPH1^[13]
DPS^[13]
Data Pointer 0 H
A15
Data Pointer 1 L
A7
Data Pointer 1 H
A15
Data Pointer 0/1 select 0
PCON
Power Control
SMOD0
TCON
Timer/Counter Control TF1
(bit addressable)
TMOD
Timer/Counter Mode
Control
GATE
TL0
Timer 0 reload L
D7
TL1
Timer 1 reload L
D7
TH0
Timer 0 reload H
D15
TH1
CKCON^[13]
Timer 1 reload H
D15
Clock Control
x
reserved
IOB^[13]
EXIF^[13]
MPAGE^[13]
Port B (bit addressable) D7
External Interrupt Flag(s) IE5
Upper Addr Byte of MOVX A15
using @R0 / @R1
reserved
SCON0
Serial Port 0 Control
(bit addressable)
SM0_0
SBUF0
AUTOPTRH1^[13]
AUTOPTRL1^[13]
Serial Port 0 Data Buffer D7
Autopointer 1 Address H A15
Autopointer 1 Address L A7
reserved
AUTOPTRH2^[13]
AUTOPTRL2^[13]
Autopointer 2 Address H A15
Autopointer 2 Address L A7
reserved
IOC^[13]
INT2CLR^[13]
INT4CLR^[13]
Port C (bit addressable) D7
Interrupt 2 clear
x
Interrupt 4 clear
x
reserved
IE
Interrupt Enable
EA
(bit addressable)
reserved
EP2468STAT^[13]
Endpoint 2,4,6,8 status EP8F
flags
EP24FIFOFLGS
[13]
Endpoint 2,4 slave FIFO 0
status flags
EP68FIFOFLGS
[13]
Endpoint 6,8 slave FIFO 0
status flags
reserved
AUTOPTRSETUP^[13] Autopointer 1&2 setup 0
IOD^[13]
Port D (bit addressable) D7
IOE^[13]
Port E
D7
(NOT bit addressable)
OEA^[13]
Port A Output Enable D7
OEB^[13]
Port B Output Enable D7
OEC^[13]
Port C Output Enable D7
OED^[13]
Port D Output Enable D7
OEE^[13]
Port E Output Enable D7
reserved
IP
Interrupt Priority (bit ad- 1
dressable)
reserved
EP01STAT^[13]
Endpoint 0&1 Status
0
D6
D6
A6
A14
A6
A14
0
x
TR1
CT
D6
D6
D14
D14
x
D6
IE4
A14
SM1_0
D6
A14
A6
A14
A6
D6
x
x
ES1
EP8E
EP4PF
EP8PF
0
D6
D6
D6
D6
D6
D6
D6
PS1
0
BB 1 GPIFTRIG^{[13, 11]}
Endpoint 2,4,6,8 GPIF DONE
0
slave FIFO Trigger
BC 1 reserved
BD 1 GPIFSGLDATH^[13] GPIF Data H (16-bit mode D15
D14
only)
Note
13. SFRs not part of the standard 8051 architecture.
14. If no EEPROM is detected by the SIE then the default is 00000000.
b5
0
D5
D5
A5
A13
A5
A13
0
1
TF0
M1
D5
D5
D13
D13
T2M
D5
I²CINT
A13
SM2_0
D5
A13
A5
A13
A5
D5
x
x
ET2
EP6F
EP4EF
EP8EF
0
D5
D5
D5
D5
D5
D5
D5
PT2
0
0
D13
b4
b3
b2
0
0
0
D4
D4
A4
A12
A4
A12
0
1
TR0
M0
D4
D4
D12
D12
T1M
D4
USBNT
A12
D3
D3
A3
A11
A3
A11
0
x
IE1
GATE
D3
D3
D11
D11
T0M
D3
1
A11
D2
D2
A2
A10
A2
A10
0
x
IT1
CT
D2
D2
D10
D10
MD2
D2
0
A10
b1
0
D1
D1
A1
A9
A1
A9
0
x
IE0
M1
D1
D1
D9
D9
MD1
D1
0
A9
b0
400KHZ
Default Access
xxxxxxxx n/a
[14]
D0
D0
A0
A8
A0
A8
SEL
IDLE
IT0
M0
D0
D0
D8
D8
MD0
D0
0
A8
xxxxxxxx RW
00000111 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00110000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000001 RW
xxxxxxxx RW
00001000 RW
00000000 RW
REN_0
D4
A12
A4
A12
A4
D4
x
x
ES0
TB8_0
D3
A11
A3
A11
A3
D3
x
x
ET1
RB8_0
D2
A10
A2
A10
A2
D2
x
x
EX1
TI_0
D1
A9
A1
A9
A1
D1
x
x
ET0
RI_0
D0
A8
A0
A8
A0
D0
x
x
EX0
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
xxxxxxxx RW
xxxxxxxx W
xxxxxxxx W
00000000 RW
EP6E
EP4FF
EP8FF
EP4F
0
0
EP4E
EP2PF
EP6PF
EP2F
EP2EF
EP6EF
EP2E
EP2FF
EP6FF
01011010 R
00100010 R
01100110 R
0
0
APTR2INC APTR1INC APTREN 00000110 RW
D4
D3
D2
D1
D0
xxxxxxxx RW
D4
D3
D2
D1
D0
xxxxxxxx RW
D4
D3
D2
D1
D0
00000000 RW
D4
D3
D2
D1
D0
00000000 RW
D4
D3
D2
D1
D0
00000000 RW
D4
D3
D2
D1
D0
00000000 RW
D4
D3
D2
D1
D0
00000000 RW
PS0
PT1
PX1
PT0
PX0
10000000 RW
0
0
EP1INBSY EP1OUTBS EP0BSY 00000000 R
Y
0
0
RW
EP1
EP0
10000xxx brrrrbbb
D12
D11
D10
D9
D8
xxxxxxxx RW
Document #: 38-08032 Rev. *M
Page 34 of 62
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