CY7C63722 Datasheet, PDF (34/58 Pages) Cypress Semiconductor – enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller

FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture A Falling Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture B Rising Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42)
Bit #
7
6
5
4
3
2
1
0
Bit Name
Capture B Falling Data
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43)
Bit #
7
Bit Name
Read/Write
-
Reset
0
6
5
Reserved
-
-
0
0
4
3
2
1
0
Capture B
Falling
Event
Capture B
Rising
Event
Capture A
Falling
Event
Capture A
Rising
Event
-
R
R
R
R
0
0
0
0
0
Bit [7:4]: Reserved.
Figure 19-6. Capture Timer Status Register (Address 0x45)
Bit [3:0]: Capture A/B, Falling/Rising Event
These bits record the occurrence of any rising or falling edges on the capture GPIO pins. Bits in this register are cleared by
reading the corresponding data register.
1 = A rising or falling event that matches the pin’s rising/falling condition has occurred.
0 = No event that matches the pin’s rising or falling edge condition.
Because both Capture A events (rising and falling) share an interrupt, user’s firmware needs to check the status of both
Capture A Falling and Rising Event bits to determine what caused the interrupt. This is also true for Capture B events.
Bit #
Bit Name
7
First Edge
Hold
Read/Write
R/W
Reset
0
6
5
4
Prescale Bit [2:0]
R/W
R/W
R/W
0
0
0
3
Capture B
Falling
Int Enable
R/W
0
2
Capture B
Rising
Int Enable
R/W
0
1
Capture A
Falling
Int Enable
R/W
0
0
Capture A
Rising
Int Enable
R/W
0
Figure 19-7. Capture Timer Configuration Register (Address 0x44)
Bit 7: First Edge Hold
1 = The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read. Subsequent
edges are ignored until the Capture Timer Data Register is read.
Document #: 38-08022 Rev. **
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